Memory-mapped AXI write hangs entire board

I’m running PYNQ v2.5 on a PYNQ Z-2 and am trying to write to a memory-mapped Xilinx AXI-Stream FIFO connected via a full AXI4 bus. Whenever I write a transaction to the IP block, the board hangs completely and only a power cycle manages to reset it. As far as I understand, this is probably caused by the AXI transaction not receiving the proper acknowledgement. In order to debug this further, I would like to use a watchdog on the AXI Master or some sort of equivalent mechanism to ensure that a failed write doesn’t necessitate a full restart. Is there a way to do this on the PYNQ Z-2?

Attached is the code I am using and a screenshot of the vivado block diagram.

ovlr = Overlay("proc_sys_0.bit")

# AXIS FIFO drivers
ISR_ADDR = 0x0*4
IER_ADDR = 0x4*4
TDFR_ADDR = 0x8*4
TDFD_ADDR = 0x10*4
TFLR_ADDR = 0x14*4
SRR_ADDR = 0x28*4

class axi_fifo:
    def __init__(self):
        print("Initializing AXI FIFO stream device...")
        self.device = ovlr.axi_fifo_mm_s_0

        print("Device Initialized.")
    def reset(self):
        print("Resetting interrupt register")
        self.device.write(ISR_ADDR,0xFFFFFFFF) # <- THIS WORKS FOR SOME REASON
        print("New interrupt register:", # <- BUT ALL OF THESE CRASH THE SYSTEM
        print("Interrupt enable status:", # <- BUT ALL OF THESE CRASH THE SYSTEM
        print("FIFO vacancy status:", # <- BUT ALL OF THESE CRASH THE SYSTEM


Hi @plasmidon,

The AXI4-Lite interface of the IP is not connected, the commands you are trying to write rely on this interface.


I was under the impression that the full AXI interface would substitute for the lite interface when I instantiated the IP block. I will try connecting everything up. Thanks for the heads up.