Modifying the base ZCU208 design from RFSoC PYNQ

Hey guys! @skalade @marioruiz ,
I am trying to modify the base design according to my needs.
I want to stream from one PLL to all the other tiles, see the attached picture.
However, when I load the bit file via the PYNQ library, I do not see the PLL is disabled by some tiles and of course is not Locked.

Can someone give me a direction on where I should start figuring out a solution?

Thanks a lot!


I had the same problem when I ported the publicly available ZCU216 project to the ZCU208 (this was before the ZCU208 was officially supported by PYNQ). My system clocking options look like the following graphic. Can you get the Python code to program the CLK104 board with TICPROS files, and see both PLL LEDs lit on the CLK104? That would prove in the SPI bus configuration with the I2C bus to both classes of TI clock chips (the LMK and LMX’s). Are you using the LMK or the LMX’s, and if the latter you do have the SMAs connected from the CLK104 to the ZCU208 ADC/DAC clocking inputs? Did you build PetaLinux yourself, and you’re sure you have the xrfclk and xrfdc packages (like the following spec file)?

ARCH_ZCU208 := aarch64
BSP_ZCU208 := xilinx-zcu208-v2020.2-final.bsp
STAGE4_PACKAGES_ZCU208 := pynq xrfclk xrfdc xsdfec ethernet

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Hey John
Thanks for responding and helping.
I booted ZCU208 from the 3.0.1 image that’s available at PYNQ - Python productivity for Zynq - Board.
Regarding your question, yes, I already connected the CLK104 board to the clock on the ZCU208.
So I have the base bitstream, which comes with it, and I already checked if I get I and Q from the data converters. It worked fine. Just after modifying the design to work with one PLL, It fails.
All the packages you have mentioned exist in the Jupyter environment, so yes, they are already built.

Thanks a lot!