Wrong PL1 fabric clock generation from Zynq RFSoC (ZCU208)

I am using ZCU208 RFSoC board and PYNQ 3.0.1 board image. I am trying to configure PL fabric clock (FCLK1 to be exact) from my python program but the generated clock is not of desired frequency (e.g. 187.498 MHz instead of 200 MHz, 214.283 MHz instead of 225 MHz).

In my design, I choose RPLL as the reference PLL source for PL1 clock but it seems the default image uses IOPLL as the reference PLL (I see the exact wrong frequencies if I select IOPLL in the configuration wizard) and my design settings doesn’t override Zynq settings in the default base image. It there any workaround to do it or do I have to modify and recreate the base ZCU208 PYNQ image?

That setting is configured at boot time, so you would need to modify or rebuild the PYNQ image.