Problem to upload the .bit file

Hi everyone,

I am using the PYNQ Z2.
I created a folder in this folder I put 3 files :

I created a python fil and coded :

from pynq import Overlay

I have this error :

CacheMetadataError Traceback (most recent call last)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in BitstreamHandler.get_parser(self, partial)
251 try:
→ 252 parser = self._get_cache()
253 except CacheMetadataError:

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in BitstreamHandler._get_cache(self)
227 else:
→ 228 raise CacheMetadataError(f"No cached metadata present")

CacheMetadataError: No cached metadata present

During handling of the above exception, another exception occurred:

IndexError Traceback (most recent call last)
Input In [1], in <cell line: 2>()
1 from pynq import Overlay
----> 2 overlay=Overlay(‘/home/xilinx/jupyter_notebooks/Radar_Project/design_2.bit’)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/, in Overlay.init(self, bitfile_name, dtbo, download, ignore_version, device, gen_cache)
315 super().init(bitfile_name, dtbo, partial=False, device=device)
317 self._register_drivers()
→ 319 self.device.set_bitfile_name(self.bitfile_name)
320 self.parser = self.device.parser
322 self.ip_dict = (
323 self.gpio_dict
324 ) = (
325 self.interrupt_controllers
326 ) = self.interrupt_pins = self.hierarchy_dict = dict()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in Device.set_bitfile_name(self, bitfile_name)
116 def set_bitfile_name(self, bitfile_name: str) → None:
117 self.bitfile_name = bitfile_name
→ 118 self.parser = self.get_bitfile_metadata(self.bitfile_name)
119 self.mem_dict = self.parser.mem_dict
120 self.ip_dict = self.parser.ip_dict

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in EmbeddedDevice.get_bitfile_metadata(self, bitfile_name, partial)
689 def get_bitfile_metadata(self, bitfile_name:str, partial:bool=False):
→ 690 parser = _get_bitstream_handler(bitfile_name).get_parser(partial=partial)
691 if parser is None:
692 raise RuntimeError(“Unable to find metadata for bitstream”)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in BitstreamHandler.get_parser(self, partial)
252 parser = self._get_cache()
253 except CacheMetadataError:
→ 254 parser = RuntimeMetadataParser(Metadata(input=self._filepath.with_suffix(“.hwh”)))
255 except:
256 raise RuntimeError(f"Unable to parse metadata")

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/metadata/, in RuntimeMetadataParser.init(self, md)
50 self.dtbo_data = None
51 self.systemgraph =
—> 52 self.ps_name = list(md.get_processing_systems().keys())[0]
53 = md.get_processing_systems()[self.ps_name]
54 self.family_ps =

IndexError: list index out of range

I followed the documentation, some tutorials… I don’t understand.

Thanks for your help guys !

Hi @symbole,

Welcome to the community!

Could you share your design_2.hwh file so I can take a look? It looks like it’s struggling to find the processing system in your design.

All the best,

Hi stf,
Thanks a lot for your reply !

design_2.hwh (84.8 KB)


No problem at all @symbole :slight_smile:

Looking at the modules in your HWH file it looks like you’re missing the Zynq Processing system IP block, which explains why Pynq couldn’t find it.

When building your block diagram in Vivado you need to make sure that you add a Zynq 7000 processing system IP to the block design.

Make sure to run “Run Block Automation” once you’ve added the processing system to you block diagram.

If you want to be able to access the AXI registers of various IP from within PYNQ you’ll need to connect them up to the processing system in Vivado.

All the best,

Wow ! Thanks a lot. It was a question that I asked to myself few days ago. Because when I simulate the system in the “Open hardware Manager” it works. But when I export the design and the bitstream it doesn’t work on jupyter.

When I will add the ZYNQ processor IP and I will click on the “Run Block Automation” the wired between the processor and the hdmi diagram will be automatic ?

Thanks a lot,

Ah great, glad to hear that explained the issue.

No, unfortunately, connecting up the rest of the system to the processing system wont be done in the block automation. The block automation looks for presets for the board you’ve specified, such as DDR width/speed etc, and applies that to the processing system block.

There is another wizard that you could try the “Run Connection Automation” which can be used to connect up bus interfaces in block design. More details here

All the best,

Hi @stf ,

Thanks for your last answer.

I did what you said. My model does include zynq now. I don’t have any errors in my modele in Vivado and I exported the bitstream.

As you can see on the pictures below I followed the documentation.
I have new errors “Could not find IP or hierarchy video in overlay”. I searched on many websites but can’t find the source of the problem.

Can you help me ?

Thanks a lot,