Overlay load fail: No cached metadata present

I execute a cell with:
from pynq import Overlay
from pynq import allocate
import xrfclk
import xrfdc
ol = Overlay(“./RFADC_DMA2.bit”)

The current directory contains the above bit file plus RFADC_DMA2.hwh (from …**.gen/sources_1/bd/mpsoc_preset/hw_handoff/ ) and RFADC_DMA2.tcl (created by exporting the block diagram) from my Vivado project (2023.2).
Anyone suggest what I am missing?
thanks.


CacheMetadataError Traceback (most recent call last)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:252, in BitstreamHandler.get_parser(self, partial)
251 try:
→ 252 parser = self._get_cache()
253 except CacheMetadataError:

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:228, in BitstreamHandler._get_cache(self)
227 else:
→ 228 raise CacheMetadataError(f"No cached metadata present")

CacheMetadataError: No cached metadata present

During handling of the above exception, another exception occurred:

MetadataObjectNotFound Traceback (most recent call last)
Input In [42], in <cell line: 5>()
3 import xrfclk
4 import xrfdc
----> 5 ol = Overlay(“./RFADC_DMA2.bit”)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py:319, in Overlay.init(self, bitfile_name, dtbo, download, ignore_version, device, gen_cache)
315 super().init(bitfile_name, dtbo, partial=False, device=device)
317 self._register_drivers()
→ 319 self.device.set_bitfile_name(self.bitfile_name)
320 self.parser = self.device.parser
322 self.ip_dict = (
323 self.gpio_dict
324 ) = (
325 self.interrupt_controllers
326 ) = self.interrupt_pins = self.hierarchy_dict = dict()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/device.py:118, in Device.set_bitfile_name(self, bitfile_name)
116 def set_bitfile_name(self, bitfile_name: str) → None:
117 self.bitfile_name = bitfile_name
→ 118 self.parser = self.get_bitfile_metadata(self.bitfile_name)
119 self.mem_dict = self.parser.mem_dict
120 self.ip_dict = self.parser.ip_dict

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:690, in EmbeddedDevice.get_bitfile_metadata(self, bitfile_name, partial)
689 def get_bitfile_metadata(self, bitfile_name:str, partial:bool=False):
→ 690 parser = _get_bitstream_handler(bitfile_name).get_parser(partial=partial)
691 if parser is None:
692 raise RuntimeError(“Unable to find metadata for bitstream”)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:254, in BitstreamHandler.get_parser(self, partial)
252 parser = self._get_cache()
253 except CacheMetadataError:
→ 254 parser = RuntimeMetadataParser(Metadata(input=self._filepath.with_suffix(“.hwh”)))
255 except:
256 raise RuntimeError(f"Unable to parse metadata")

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/metadata.py:40, in Metadata(input)
38 if os.path.isfile(input):
39 if str(input).endswith(“.hwh”):
—> 40 return HwhFrontend(_hwhfile=input)
41 elif str(input).endswith(“.xsa”):
42 return XsaFrontend(input=input)

File :25, in init(self, name, type, generic_type, _parent, _children, ref, ext, _timestamp, hierarchy_name, ports, parameters, blocks, modules, busses, _hierarchies, _hwhfile, _element_tree, _root, _logical2physical_portmap, _physical2logical_portmap, _logical2physical_extern_pm, _physical2logical_extern_pm)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:219, in HwhFrontend.post_init(self)
207 “”"
208 Performs the parsing of the hwh into the metadata model
209 * checks to see if the hwhfile is an XML string or a
(…)
216 * Performs a connectivity pass
217 “”"
218 if self._hwhfile != “”:
→ 219 self.parse()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:241, in HwhFrontend.parse(self)
238 self._create_external_ports()
240 self.resolve_addressing()
→ 241 self.connect_signals()
243 self.refresh()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:657, in HwhFrontend.connect_signals(self)
653 dst_signal = dst_core.lookup(
654 f"{dst_portname}[port]:{dst_signame}[signal]"
655 )
656 else:
→ 657 dst_signal = dst_core.lookup(
658 f"{c_dst}[port]:{c_dst}[signal]"
659 )
661 if isinstance(signal, Signal) and isinstance(dst_signal, Signal):
662 signal.connect(dst_signal)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/models/metadata_object.py:185, in MetadataObject.lookup(self, ref)
183 return obj
184 else:
→ 185 raise MetadataObjectNotFound(
186 f"{ref} cannot be found in {self.ref} children={self._children.keys()}"
187 )

MetadataObjectNotFound: s_axis_s2mm_tlast[port]:s_axis_s2mm_tlast[signal] cannot be found in mpsoc_preset:axi_dma_0[block] children=dict_keys([‘C_DLYTMR_RESOLUTION[parameter]’, ‘C_ENABLE_MULTI_CHANNEL[parameter]’, ‘C_FAMILY[parameter]’, ‘C_INCLUDE_MM2S[parameter]’, ‘C_INCLUDE_MM2S_DRE[parameter]’, ‘C_INCLUDE_MM2S_SF[parameter]’, ‘C_INCLUDE_S2MM[parameter]’, ‘C_INCLUDE_S2MM_DRE[parameter]’, ‘C_INCLUDE_S2MM_SF[parameter]’, ‘C_INCLUDE_SG[parameter]’, ‘C_INCREASE_THROUGHPUT[parameter]’, ‘C_MICRO_DMA[parameter]’, ‘C_MM2S_BURST_SIZE[parameter]’, ‘C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH[parameter]’, ‘C_M_AXIS_MM2S_TDATA_WIDTH[parameter]’, ‘C_M_AXI_MM2S_ADDR_WIDTH[parameter]’, ‘C_M_AXI_MM2S_DATA_WIDTH[parameter]’, ‘C_M_AXI_S2MM_ADDR_WIDTH[parameter]’, ‘C_M_AXI_S2MM_DATA_WIDTH[parameter]’, ‘C_M_AXI_SG_ADDR_WIDTH[parameter]’, ‘C_M_AXI_SG_DATA_WIDTH[parameter]’, ‘C_NUM_MM2S_CHANNELS[parameter]’, ‘C_NUM_S2MM_CHANNELS[parameter]’, ‘C_PRMRY_IS_ACLK_ASYNC[parameter]’, ‘C_S2MM_BURST_SIZE[parameter]’, ‘C_SG_INCLUDE_STSCNTRL_STRM[parameter]’, ‘C_SG_LENGTH_WIDTH[parameter]’, ‘C_SG_USE_STSAPP_LENGTH[parameter]’, ‘C_S_AXIS_S2MM_STS_TDATA_WIDTH[parameter]’, ‘C_S_AXIS_S2MM_TDATA_WIDTH[parameter]’, ‘C_S_AXI_LITE_ADDR_WIDTH[parameter]’, ‘C_S_AXI_LITE_DATA_WIDTH[parameter]’, ‘Component_Name[parameter]’, ‘c_addr_width[parameter]’, ‘c_dlytmr_resolution[parameter]’, ‘c_enable_multi_channel[parameter]’, ‘c_include_mm2s[parameter]’, ‘c_include_mm2s_dre[parameter]’, ‘c_include_mm2s_sf[parameter]’, ‘c_include_s2mm[parameter]’, ‘c_include_s2mm_dre[parameter]’, ‘c_include_s2mm_sf[parameter]’, ‘c_include_sg[parameter]’, ‘c_increase_throughput[parameter]’, ‘c_m_axi_mm2s_data_width[parameter]’, ‘c_m_axi_s2mm_data_width[parameter]’, ‘c_m_axis_mm2s_tdata_width[parameter]’, ‘c_micro_dma[parameter]’, ‘c_mm2s_burst_size[parameter]’, ‘c_num_mm2s_channels[parameter]’, ‘c_num_s2mm_channels[parameter]’, ‘c_prmry_is_aclk_async[parameter]’, ‘c_s2mm_burst_size[parameter]’, ‘c_s_axis_s2mm_tdata_width[parameter]’, ‘c_sg_include_stscntrl_strm[parameter]’, ‘c_sg_length_width[parameter]’, ‘c_sg_use_stsapp_length[parameter]’, ‘c_single_interface[parameter]’, ‘EDK_IPTYPE[parameter]’, ‘C_BASEADDR[parameter]’, ‘C_HIGHADDR[parameter]’, ‘ADDR_WIDTH[parameter]’, ‘ARUSER_WIDTH[parameter]’, ‘AWUSER_WIDTH[parameter]’, ‘BUSER_WIDTH[parameter]’, ‘CLK_DOMAIN[parameter]’, ‘DATA_WIDTH[parameter]’, ‘FREQ_HZ[parameter]’, ‘HAS_BRESP[parameter]’, ‘HAS_BURST[parameter]’, ‘HAS_CACHE[parameter]’, ‘HAS_LOCK[parameter]’, ‘HAS_PROT[parameter]’, ‘HAS_QOS[parameter]’, ‘HAS_REGION[parameter]’, ‘HAS_RRESP[parameter]’, ‘HAS_WSTRB[parameter]’, ‘ID_WIDTH[parameter]’, ‘INSERT_VIP[parameter]’, ‘MAX_BURST_LENGTH[parameter]’, ‘NUM_READ_OUTSTANDING[parameter]’, ‘NUM_READ_THREADS[parameter]’, ‘NUM_WRITE_OUTSTANDING[parameter]’, ‘NUM_WRITE_THREADS[parameter]’, ‘PHASE[parameter]’, ‘PROTOCOL[parameter]’, ‘READ_WRITE_MODE[parameter]’, ‘RUSER_BITS_PER_BYTE[parameter]’, ‘RUSER_WIDTH[parameter]’, ‘SUPPORTS_NARROW_BURST[parameter]’, ‘WUSER_BITS_PER_BYTE[parameter]’, ‘WUSER_WIDTH[parameter]’, ‘HAS_TKEEP[parameter]’, ‘HAS_TLAST[parameter]’, ‘HAS_TREADY[parameter]’, ‘HAS_TSTRB[parameter]’, ‘LAYERED_METADATA[parameter]’, ‘TDATA_NUM_BYTES[parameter]’, ‘TDEST_WIDTH[parameter]’, ‘TID_WIDTH[parameter]’, ‘TUSER_WIDTH[parameter]’, ‘S_AXI_LITE[port]’, ‘M_AXI_SG[port]’, ‘M_AXI_S2MM[port]’, ‘S_AXIS_S2MM[port]’, ‘S_AXIS_STS[port]’, ‘axi_resetn[port]’, ‘m_axi_s2mm_aclk[port]’, ‘m_axi_sg_aclk[port]’, ‘s2mm_introut[port]’, ‘s2mm_prmry_reset_out_n[port]’, ‘s2mm_sts_reset_out_n[port]’, ‘s_axi_lite_aclk[port]’])

Hi,
Which board are you using?

Can you please provide the Vivado architecture you are using (.tcl, .bit and .hwh)?

Hi,
I am using the ZCU208 and starting to learn about Pynq. I had tried a few years ago and couldn’t get things to work so have been using KoheronSDK for about a decade (which incidentally works very nicely). I have attached the files in questionRFADC_DMA2.hwh (494.0 KB)
RFADC_DMA2.tcl (38.0 KB)
Unfortunately the .bit file looks too be to big to post, but I guess can be generated from the tcl file. I was trying to connect up the RFSoC ADC to a DMA block to try reading ADC data. I have since started a new design from scratch and that now seems to load OK, so not sure what the issue was. The error messages from Xilinx software don’t seem to be very helpful (or at least you need to be a super sleuth to figure them out lol). cheers G