Problem with Overlay package

Support
1

I’m using PYNQ with ZC706 board. I’ve used the official instructions to build the image for this board. (The Pynq-z1 base overlay is used to make the .bit file compatible with the ZC706 board)

When I want to run the following code (after some imports!):

print('start')    
OVERLAY_PATH = 'overlay.bit'
overlay = Overlay(OVERLAY_PATH)
dma = overlay.axi_dma_0

xlnk = Xlnk()
nn_ctrl = MMIO(0x43c00000, length=1024)
print('Got nn_ctrl!')

I get the following error:

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py:299: UserWarning: Users will not get PARAMETERS / REGISTERS information through TCL files. HWH file is recommended.
  warnings.warn(message, UserWarning)

---------------------------------------------------------------------------
TimeoutError                              Traceback (most recent call last)
TimeoutError: [Errno 110] Connection timed out

During handling of the above exception, another exception occurred:

TimeoutError                              Traceback (most recent call last)
<ipython-input-2-829759b192df> in <module>()
      1 print('start')
      2 OVERLAY_PATH = 'overlay.bit'
----> 3 overlay = Overlay(OVERLAY_PATH)
      4 dma = overlay.axi_dma_0
      5 

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py in __init__(self, bitfile_name, download, ignore_version)
    313 
    314         if download:
--> 315             self.download()
    316 
    317         self.__doc__ = _build_docstring(self._ip_map._description,

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py in download(self, partial_bit)
    377                     Clocks.set_pl_clk(i)
    378 
--> 379             super().download()
    380             PL.reset(self.parser)
    381         else:

/usr/local/lib/python3.6/dist-packages/pynq/pl.py in download(self)
   1943             fd.write(flag)
   1944         with open(self.BS_FPGA_MAN, 'w') as fd:
-> 1945             fd.write(self.binfile_name)
   1946 
   1947         # update PL information

TimeoutError: [Errno 110] Connection timed out

Also the INIT led on the board turns into RED

56%20AM
56%20AM1080×810 43 KB

Unfortunately I have no clue how to solve this issue. Any help is welcomed.

2

This looks like an issue with how the FPGA manager device and the bitstream are interacting - for some reason the FPGA download is failing. Are you able to program the bitstream via JTAG from Vivado?

Peter

3

Hey Peter,
I haven’t tried that. You mean I should try to program the ‘overlay.bit’ file via JTAG? (If its necessary I can buy and try)

4

I thought that the ZC706 had a built in USB JTAG connection but it appears I was wrong. Before going there, can you run the dmesg command and see if there is something useful at the end after trying to download the bitstream?

Normally there will be a line referencing the FPGA manager downloading the bitstream - hopefully there will be more details about why it failed immediately after.

Are you also able to post your .bit file?

Peter

5

These are the output of dmesg run immediately after the failure mentioned above:

[  234.466893] fpga_manager fpga0: reading flags 0
[  234.466906] fpga_manager fpga0: writing overlay.bin to Xilinx Zynq FPGA Manager
[  236.987836] fpga_manager fpga0: Error after writing image data to FPGA
[  236.994006] fpga_manager fpga0: reading flags 0
[  236.994018] fpga_manager fpga0: writing overlay.bin to Xilinx Zynq FPGA Manager
[  239.505684] fpga_manager fpga0: Timeout waiting for PCFG_INIT
[  239.510142] fpga_manager fpga0: Error preparing FPGA for writing

I’m trying to run this project: spooNN/mnist-cnn at master · fpgasystems/spooNN · GitHub which is a CNN running on the PYNQ platform. The .bit file address: spooNN/overlay.bit at master · fpgasystems/spooNN · GitHub

6

Unfortunately, I still cannot solve this problem. Does anyone have an idea how to solve this?

7

You should be able to download a bitstream from Vivado using just a USB cable.
It would be good to try this to make sure the bitstream is correct.

You can connect a micro USB cable to the USB JTAG port.

A quick google on your error message suggest you may need a kernel patch:
https://forums.xilinx.com/t5/Configuration/Download-encrypted-bitstream-zyng7000-using-fpga-manager/td-p/962571

I’m assuming you don’t have an encrypted bitstream - this could also cause problems.

Cathal

8

The problem was the the .bit file was not built(generated) for ZC706 and instead targeted another board. Rebuilding for this board solved the problem.

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