TimeoutError: [Errno 110] Connection timed out

Support
1

I have generated the block design and exported the bitstream and the tcl file from vivado

I am trying to pass inputs through DMA and to get the output. I have attached the block design and the python code

import numpy as np
from pynq import allocate
from pynq import Overlay

I am getting the error here

overlay = Overlay(“streamingvitis.bit”)

ValueError Traceback (most recent call last)
in ()
----> 1 overlay = Overlay(“streamingvitis.bit”)
2 dma = overlay.axi_dma
3 input_buffer = allocate(shape=(16,), dtype=np.uint8)
4 output_buffer = allocate(shape=(8,), dtype=np.uint8)

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py in init(self, bitfile_name, dtbo, download, ignore_version, device)
339 self._register_drivers()
340
→ 341 self.parser = self.device.get_bitfile_metadata(self.bitfile_name)
342
343 self.ip_dict = self.gpio_dict = self.interrupt_controllers = \

/usr/local/lib/python3.6/dist-packages/pynq/pl_server/device.py in get_bitfile_metadata(self, bitfile_name)
780 else:
781 raise ValueError(“Cannot find HWH file for {}.”.format(
→ 782 bitfile_name))

ValueError:: Cannot find HWH file for /home/xilinx/jupyter_notebooks/Pynq/streamingvitis.bit.

dma = overlay.axi_dma

input_buffer = allocate(shape=(16,), dtype=np.uint8)
output_buffer = allocate(shape=(8,), dtype=np.uint8)

for i in range(5):
if(i<8):
input_buffer[i] = 1
else :
input_buffer[i] = 2

dma.sendchannel.transfer(input_buffer)
dma.recvchannel.transfer(output_buffer)
dma.sendchannel.wait()
dma.recvchannel.wait()

design_1.pdf (86.0 KB)

2

This is generated from Vivado when you generate your bitstream. Do a search on your Vivado project directory, and copy the file to your board with the .bit file.
There may be more than one HWH file. You should be able to figure out which one is the “top” HWH.

Cathal

3

After the bitstream generation was complete I had two options

  1. Exporting the bitstream file
  2. Exporting the hardware
    Where a .dsa file is exported. Where is my actual hwh and bit file exported? is it in the same directory?
4

This may depend on the version of Vivado you are using, your project name, source directory name etc.

You might find the HWH here:
[project directory]\project_name\project_name.srcs\sources_1\bd[block diagram name]\hw_handoff

I usually search for “hwh” from the top level project directory to locate this file.

Cathal

5

I have included the hwh file , tcl and bitstream. The issue i am facing is listed below. Even in the serial port communication it shows error writing data to the FPGA

TimeoutError Traceback (most recent call last)
TimeoutError: [Errno 110] Connection timed out

During handling of the above exception, another exception occurred:

TimeoutError Traceback (most recent call last)
in ()
----> 1 overlay = Overlay(“design_1_wrapper.bit”)
2 dma = overlay.axi_dma

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py in init(self, bitfile_name, dtbo, download, ignore_version, device)
353
354 if download:
→ 355 self.download()
356
357 self.doc = _build_docstring(self._ip_map._description,

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py in download(self, dtbo)
417 Clocks.set_pl_clk(i)
418
→ 419 super().download(self.parser)
420 if dtbo:
421 super().insert_dtbo(dtbo)

/usr/local/lib/python3.6/dist-packages/pynq/bitstream.py in download(self, parser)
185
186 “”"
→ 187 self.device.download(self, parser)
188
189 def remove_dtbo(self):

/usr/local/lib/python3.6/dist-packages/pynq/pl_server/device.py in download(self, bitstream, parser)
768 fd.write(flag)
769 with open(self.BS_FPGA_MAN, ‘w’) as fd:
→ 770 fd.write(bitstream.binfile_name)
771 if parser is not None:
772 self.set_axi_port_width(parser)

TimeoutError: [Errno 110] Connection timed out

6

@srinivasan74 did you solve it?