Problem with Zynq UltraScale MPSoC Cache Coherency

I am currently facing a problem with deploying a model and after tracing I found out that the problem may be related to Zynq UltraScale MPSoC Cache Coherency.

I have successfully created a custom pynqv2.6 image using a bionic agonistic file and BSP for zcu102 as this is the version currently supported by the Apache TVM DL. However, when running a test model, it got stuck at ‘load module’ with default parameters. But when the COHERENT_ACCESSES is changed to false, it runs normal but with a wrong output/prediction.

Could this possibly be a problem with the image creation phase or is there any possible support to fix this?

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