I am a beginner using PYNQ-Z2. I want to transfer data between ddr and bram, so I tried to follow this example. But when I tried to use mmio to read the bram, the kernel will die.
from pynq import Overlay
from pynq import allocate
import numpy as np
ol = Overlay("./pl_ddr.bit")
CTRL_REG=0x00
SA_REG=0x18
DA_REG=0x20
BTT_REG=0x28
cdma=ol.axi_cdma_0.mmio
sys_in1 = 0x00000000 # zynq's addr
from pynq import MMIO
sys = MMIO(sys_in1,0x14)
bram = MMIO(0xC0000000,0x14)
sys.write(0x0,1)
cdma.write(CTRL_REG,0x04)
cdma.write(SA_REG,0x00000000)
cdma.write(DA_REG,0xC0000000)
cdma.write(BTT_REG,0x4)
print(sys.read(0x0000))
print(bram.read(0x0000)) #kernel will die
cdma.write(CTRL_REG,0x04)
cdma.write(SA_REG,0xC0000000)
cdma.write(DA_REG,0x00000004)
cdma.write(BTT_REG,0x4)
print(sys.read(0x0004))
And I expect the last result should be 1, but it is a random data. So the access to BRAM is definitely failing.
Here is my block design, thanks for helping.
When I tried to transfer data with the code as follow:
cdma.write(SA_REG,0x00000000)
cdma.write(DA_REG,0x00000004)
cdma.write(BTT_REG,0x04)
print(cdma.read(0x4))
I found the result is 20514, which means there is a DMA slave error. Thanks for pointing the possible reason.
I tried to use this driver. But every time 32 bits of data are transferred, next 32 bits will be lost. For example, I transferred 0,1,2,3,4,5,6,7,8,9. I will get 0,0,2,0,4,0,6,0,8,0.
Hi @290787665,
Can you please show how the CDMA is configure?
Mario
Can you please check that your S_AXI_HP0 interface is configured to 32-bit wide. Or, change the Write/Read Data Width of the CDMA to 64.
Thank you very much!
I tried to set all interfaces(included S_AXI_HP0) to 64-bit wide, and the driver worked correctly.
All interfaces are 32-bit wide before. It seems that HP interfaces must be 64-bit right? I’m new to the PYNQ board.
The data width on the interfaces should match the data path of your IP.
May I ask how you resolved the kernel deadlock issue? I’m encountering the same problem.
