I am using pynq version 2.7 to create a vector add example. However, the results are half correct. No idea to find how to slove this problem. Have tried different hls and vivado versions.
vitis hls 2020.2, vivado 2022.2 and data width of zynq slvae HP is set 32.
I want to find what cases this problem.
Welcome to our community.
Are the 3 HP ports configured to 32 bit?
Why are you enabling cacheable?
Did you try with different element values? So the sum is different than 11 for each element in the output.
Please try with HP DATA WIDTH set to 64 bit
Thanks. I get right results with 64 bit. As for 32bit, maybe the parameter depth of maxi has some effect.
No, the Zynq 7000 is configured with 64-bit width HP ports. PYNQ is not updating these ports at runtime. For MPSoC, the bitwidth of these ports can be configured at runtime.