Hi @crypty_potato,
Unfortunately, I currently not allowed to share the files. Moreover, my design or notebook wouldn’t help your case, as I use custom designed IPs. In my design whole information is embedded on the FPGA, function only changes based on the information I want to send. I reread the whole thread again, I realized I made some mistakes. You need to change I/Q mode real->real mode. That might help, but that will change the clocks as well.
Do you mean you are using the original code in the notebooks (like in the below)?
def set_transmitter_channel(channel, enable, gain, frequency):
channel.control.enable = enable
channel.control.gain = gain
channel.dac_block.MixerSettings[‘Freq’] = frequency
set_transmitter_channel(base.radio.transmitter.channel[0], True, 0.8, 900)
set_transmitter_channel(base.radio.transmitter.channel[1], True, 0.1, 1500)
If you want to change sampling, you will also need to change the clocks of LMK and LMX clocking components. Check out RFDC Start Up Fail - ADC 0 timed out at state 7 in XRFdc_WaitForRestartClr topic. You need to use TICSPRO to change your sampling and clocks.
Feel free to reach out if you have any other questions.