Change ADC sample rate

joe052790 · October 22, 2024, 8:50am

Device: RFSoC 4x2 Kit
PYNQ Version: v3.0.1
I would like to ask if the ADC sample rate of this device can be adjusted?
I can use all 4 ADC channels normally, so the ADC sample rate is 0~2.5 GS/s.
But can I use only two ADC channels to achieve a sample rate of 1~5 GS/S?
I found this information in the RFSoC Board Files on this website:
RFSoC 4x2 | Real Digital.

matthew · October 22, 2024, 10:01am

Hi,
I think it can be adjusted via the block RF Data converter in the block design (in Vivado), you need to change some parameters in that block.

joe052790 · October 23, 2024, 7:48am

I am performing the operation of the following URL. When I come to source ./base.tcl, vivado reports a
ERROR: [Board 49-71] The board_part definition was not found for realdigital.org:rfsoc4x2:part0:1.0. The project’s board_part property was not set, but the project’s part property was set to xczu48dr-ffvg1517-2-e. Valid board_part values can be retrieved with the ‘get_board_parts’ Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

github.com

Xilinx/RFSoC-PYNQ/blob/master/docs/rfsoc_4x2_base_overlay.md

---
layout: default
---

# RFSoC 4x2 Base overlay

The `base` overlay is included in the PYNQ image for the  RFSoC 4x2 board. The purpose of the base overlay design is to allow you to get start using your board with PYNQ out-of-the-box. The base design includes a bitstream with IP to allow you to start using the RF ADCs and DACs on the board. The other main blocks are the memory controller for the PL DRAM, two PYNQ PMOD IOPs to connect to Pmod™ ports, AXI GPIO controllers, an interrupt block, and a system monitor. 

## Block Diagram

All IP are connected to the PS, and controllable from PYNQ. AXI GPIO controllers are connected to the RGB LEDs and white user LEDs, buttons and switches. The SYZYGY port is also connected to an AXI GPIO controller. An interrupt controller All these IP blocks are connected to the PS and are controllable from PYNQ. 

![](./images/rfsoc_4x2_base_overlay.png)

The PL DRAM is mapped to the PS memory map, effectively extending the amount of DRAM available to the PS. This is only intended as a simple example showing how to configure the IP for the PL DRAM. As this DRAM controller is in the PL, it will be slower to access this memory than the PS attached DRAM. It is likely in your own designs that you will make a direct connection from IP in your design to the PL DRAM.  

The SYZYGY port is connected to a simple AXI GPIO controller connected to the PS. This allows you to interact with the SYZYGY port in a very simple way using the PYNQ AXI GPIO class (which uses PYNQ MMIO). For your own designs, you will likely add your own custom IP to control the SYZYGY peripheral you are using. 


## Notebook/Python API

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matthew · October 23, 2024, 9:51am

Do you have a Vivado entreprise edition, license? RFSoC are not supported on the free standard one: (https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado/vivado-buy.html#tabs-413944f675-item-d41fa24f69-tab)

marioruiz · October 23, 2024, 10:25am

You need to install the board files in Vivado. RFSoC 4x2 Board Files and BSP | RFSoC-PYNQ

Instructions are here Install Digilent's Board Files - Digilent Reference

As @matthew mentioned, you will need a Vivado license as well.

joe052790 · October 24, 2024, 3:14am

Thanks to both of you, I have created the base design in vivado

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Change ADC sample rate

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