RFSoC 4x2 Overlay Upload Issue

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1 
import numpy as np
import socket
from pynq import Overlay
from pyftdi.ftdi import Ftdi
from aerpawFPGAController import *
from aerpawSiversController import *
from aerpawLibraryCommunications import *

fsysref = 32
fpl = 192
frfdc = 1536
decimation = 1
tagBitStream = 'v47'
tagLMK = 'v0'
tagLMX = 'v0'

bitStreamAERPAW = 'aerpawFPGA_' + str(fsysref) \
                                     + '_' + str(fpl) \
                                     + '_' + str(frfdc) \
                                     + '_D' + str(decimation) \
                                     + '_' + tagBitStream + '.bit'
lmkParameters = {'fsysref': fsysref, 'fpl': fpl, 'tag': tagLMK}
lmxParameters = {'fpl': fpl, 'frfdc': frfdc, 'tag': tagLMX}          

folderAERPAW = '/home/xilinx/jupyter_notebooks/aerpaw/'
print("Hello AERPAW User")
print('=================================')
print('=================================')
print('AERPAW folder: ' + folderAERPAW)
print('FPGA bitsteam: ' + bitStreamAERPAW)
print('=================================')
print('=================================')

if True:
    print("Starting the FPGA controller")
    overlay = Overlay(folderAERPAW+bitStreamAERPAW, ignore_version=True)
    fgpaControllerObj = fgpaController(overlay,lmkParameters,lmxParameters)
    print("FPGA controller is loaded.")

Above is my code. However, I am getting this error that I do not know how to resolve:

OSError Traceback (most recent call last)
OSError: [Errno 22] Invalid argument

During handling of the above exception, another exception occurred:

OSError Traceback (most recent call last)
in
34 if True:
35 print(“Starting the FPGA controller”)
—> 36 overlay = Overlay(folderAERPAW+bitStreamAERPAW, ignore_version=True)
37 fgpaControllerObj = fgpaController(overlay,lmkParameters,lmxParameters)
38 print(“FPGA controller is loaded.”)

/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/overlay.py in init(self, bitfile_name, dtbo, download, ignore_version, device)
352
353 if download:
→ 354 self.download()
355
356 self.doc = _build_docstring(self._ip_map._description,

/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/overlay.py in download(self, dtbo)
418 Clocks.set_pl_clk(i)
419
→ 420 super().download(self.parser)
421 if dtbo:
422 super().insert_dtbo(dtbo)

/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/bitstream.py in download(self, parser)
185
186 “”"
→ 187 self.device.download(self, parser)
188
189 def remove_dtbo(self):

/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/pl_server/embedded_device.py in download(self, bitstream, parser)
594 fd.write(str(flag))
595 with open(self.BS_FPGA_MAN, ‘w’) as fd:
→ 596 fd.write(bitstream.binfile_name)
597
598 self.set_axi_port_width(parser)

OSError: [Errno 22] Invalid argument

I have uploaded the bitstream (.bit) file and the accompanying .hwh file to the appropriate folder: /home/xilinx/jupyter_notebooks/aerpaw

I do not have much else detail to provide for now, but any help would be appreciated. Thank you!

2

Hi @yichyun,

Welcome to the PYNQ community.

What device did you use in the Vivado project? This error is could be a mismatch of the device in Vivado and the actual board.

Mario

3

That was indeed a problem. I am using an RFSoC 4x2 board but I did not choose the appropriate project device when I ran synthesis on Vivado. Will update soon.

Thank you Mario for the response!

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