RFsoc4x2 EN_VCCpSYZYGY_VIO where is this connected?

Support
1

board is RFsoc4x2 schematic
RELEASED.RFSoC_4X2_Gen3_V2I1_SCH_Prototype_2021-12-17_V2.pdf
and see that the SYZYGY VIO voltage is provided by IC74 (page 42 POWER
VI: SYZYGY) and the IC74 enable pin is connected to EN_VCCpSYZYGY_VIO
which I can’t find anywhere in the schematic. Since the VIO voltage
does work something must be driving this. What?

PS: converting the pdf to text and grep doesn’t find it…
I want to keep VIO off until the voltage is set correctly.

2

Hi @michael729

Welcome to the PYNQ community!

I would suggest reaching out to Real Digital directly to ask them 4x2 schematic-related questions

3

Good idea. I sent them a query Thursday. In the meantime I’ve tried a
different approach – look at the gerbers and follow the trace for the
VIO switcher enable line.

Refering to ‘RFSoC_4X2_Reference Designators.pdf’ I found the switcher
IC75 on the back side of the 4x2 board. Viewing the gerbers in gerbv
the chip is viewed from the top of the board which is the bottom since
it’s on the back side. Finding the enable pin (middle in the bottom)
I can see holes in many layers at the logical point for a layer switch.

However no layer I see seems to have a trace there.

Possibly I missed it or it isn’t visible with gerbv. Or worse, possibly
the same process which created the schematic without a visible connection
to the enable pin also created the gerbers I’m looking at. They appear
to match.

my prevous message sent to Real Digital:

I’m looking at the RFSoC4x2 board schematic:

RELEASED.RFSoC_4X2_Gen3_V2I1_SCH_Prototype_2021-12-17_V2.pdf

On page 42 POWER VI: IC74 the SYZYGY VIO switching regulator enable pin is
driven by the signal EN_VCCpSYZYGY_VIO. I’m unable to find this anywhere
else on any page on the schematic. It must be driven by something other
than the 100K pull down shown on the schematic as the VIO voltage does
turn on.

And it turns on to over (by a bit) 3.3 volts as the DAC value at power
up is zero (lower here means higher VIO voltage as the DAC drives the
switching regulator feedback pin).

I want to keep VIO off until the VIO voltage can be set correctly for
the current usage of the SYZYGY port.

I’m interested in any information you have about this including what
the EN_VCCpSYZYGY_VIO pin is connected first and any hints you have on
how to control it (PS or PL pins or ?).

PS: I tried converting the PDF to text and using grep but only find
that one reference.

PS: Not important to me but you might want to know that the schematic
page 3 power diagram shows the SYZYGY VIO tps563240 being powered
with 5V from an LTC3636 but the schematic on page 42 shows the
tps563240 input labeled VCCp12V0.