SYZYGY VIO on RFSoC 4x2

[yacremann]

Dear all,

We have an RFSoC 4x2 board (using PYNQ 3.01) and are developing our own SYZYGY board. On the SYZYGY board we implemented a correctly programmed SYZYGY DNA microcontroller, which is supposed to set the VIO voltage to 2.5V (as we are using the LVDS lines to the FPGA). We also tested our SYZYGY board on an Eclypse board, where the VIO voltage is set correctly.
However, on the RFSoC 4x2 board, the VIO voltage rises immediately to 3.3V during booting. We can change it to the correct voltage using a Jupyter notebooks, but initially, it goes to 3.3V. Is there a way to prevent this from happening, so it uses the SYZYGY DNA protocol to determine the correct VIO voltage?

If there is no way to change VIO to 2.5V on boot: Is there a danger for the LVDS transceiver on the FPGA?

Thanks a lot!

Best,
Yves

[godfly]

In my opinion, the most robust way to deal with this is: to take 3.3V on SYZYGY pin 40 as input and feed that into an LDO with 2.5V output. It is always good to use an LDO to ensure the level of your supply voltage is correct.

Here is a reference schematics, where the bypass capacitors are omitted:

It is recommended to wire VCCp3V3 on pin 40 to the LDO, rather than VCCpSYZYGY_VIO on pin 39, as LDO always expects a higher input level than the output level.

[yacremann]

Thanks a lot! Yes, this is something I was considering too. However, I am a bit concerned that initially, the IO block of the FPGA is also supplied by VIO to 3.3V. One solution I am considering is to use the following sequence to start up:

1.) On boot, the base overlay sets the IO levels of the SYZYGY pins to 3.3V LVCMOS as inputs

2.) Set the VIO voltage to 2.5V through the PYNQ Python interface (using the base overlay)

3.) Load our own overlay, which sets the IO pins for the SYZYGY interface to LVDS (in the constrains file) which requires a supply voltage of 2.5V for the IO block of the FPGA

I guess (and hope) this is safe. At the same time, I fully agree, a separate voltage regulator for VIO on the SYZYGY board is a good idea.

Best,

Yves

[godfly]

Oh I see. You are concerned about the VCCO of bank 84 and 87 because they are powered by VIO.

Actually, it is absolutely fine to have VCCO=3.3V when using LVDS_25 IO standards as inputs. See this link.

However, if some of the SYZYGY pins are outputs from the FPGA, then VCCO must be 2.5V.

Since we are talking about RFSoC 4x2, we don’t have to worry about this, because the SYZYGY pins are connected to HD banks (84 and 87), which only allow LVDS_25 inputs, not outputs.

[godfly]

I forgot to mention that the on-chip termination has to be disabled if VCCO is not 2.5V for LVDS_25 inputs.

The 10 differential pairs (D0-D7, C2P/P2C_CLK) are already terminated on the board, so there isn’t a problem for them.

However, the remaining 12 pins (S16-S27) are not terminated on the board (nor terminated on the chip), meaning they can not be used as differential pairs in this case. Terminating them on the SYZYGY pod, on the other hand, may lead to signal integrity issues.

My conclusion: if we want to use S16-S27 as LVDS_25 input differential pairs, then we have to set VCCO to 2.5V. Otherwise (for D0-D7, C2P_CLK and P2C_CLK) it is fine to have VCCO=3.3V.

[yacremann]

Ah, thanks a lot, this helps me a lot!

It is very kind of you to give me such great, detailed information concerning this issue! I now feel confident designing our board accordingly.

I wish you a very nice weekend!

Best regards,

Yves