As far as I remember this code is not compatible with slave mode and you have to change FIFO clear settings and might be other registers as well to make it work. Also, there was a bug in this IP (while i was working with it) of receiving inconsistent data (sometimes 1, sometimes 2 cycles) while reading slave, which I could not solve. This might have been fixed by now. I am no help here, I just can suggest going through the documentation and making appropriate changes.
