So I am adding in a TPG IP in the base overlay as replacement to hdmi input. The maximum data width of the TPG is set to 16 to match the input of the pixel_pack IP. I program the TPG registers to output a green screen and use the hdmi_video_pipeline as a guide. However I did not see any output once I tie the readchannel and writechannel of the VDMA. Attached is the change I did to the base overlay block diagram and the python code to control the TPG. Any help is appreciated.TPG Mux Select Test.ipynb (5.2 KB)
Can you attach the tcl file for your block design so I can quickly reproduce it and have a look?