PYNQ: PYTHON PRODUCTIVITY

Problem with Modifying Base Overlay

I added in a test pattern generator to the base overlay. Instead of having the output of the color_convert IP output went into the pixel_pack IP input, I have the tpg output went into the input instead. Bitstream built fine and I copied the .bit, .tcl, and .hwh to be used in Python. I did the import and instantiate the overlay object. When I did overlay?, I did not see v_tpg_0 under video/hdmi_in/. Am I missing something?

If the IP is the block design it should be showing up in the hierarchy. Are you able to post the tcl and hwh file you are using so we can get a better idea of what’s going on?

Peter

The tpg IP is a xilinx provided IP. I do see the tpg IP in the hierarchy. One more thing I want to note is that I disconnect the output of the color_convert IP in the hdmi_in block but since I want to test out the output of the tpg. However I do not think this create any problem since bitstream build fine. Attached is the .tcl & .hwh files. base.zip (195.7 KB)

Does the IP has an address? The ip_dict will only show addressable IPs, not including those that users cannot control. How do you plan to play with this IP?

If you only want to make sure that IP is in your design and gets parsed, have you tried hierarchy_dict?

I think I have it solved. I did not add the tpg to the PS memory map. I thought the tool will automatically do this for me when I connect the slave control port of the IP to the AXI interconnect, which is connected to the PS M_AXI_HPM0_LPD.