Hi Mario,
First of all, thank you very much for your response!
I would like to mention that I have never worked with Vitis HLS before, but following your advice I have tried to implement it. Mainly, I have been guiding myself through this series of tutorials: PYNQ HLS Stream IP Tutorial, and by checking the example repository you kindly shared.
To summarize my situation:
- I have created the IP block in Vitis HLS.
- I integrated it into my hardware design, connecting it properly between the XADC and the AXI DMA.
- Then I generated the bitstream and tried to work with it from a PYNQ Jupyter Notebook.
However, the problem arises in PYNQ:
I am unable to properly access the IP from Python. When I try to interact with it, it does not even recognize it. Additionally, I tried to manually send a random voltage value (without using the new IP) and it did not work either, which makes sense because the IP is not being correctly initialized or accessed from Python
Would you mind suggesting what might be missing in my design or flow?
-
Vitis HLS source code
-
BD in Vivado
-
How I am trying to interact with the IP from PYNQ
Thanks a lot again for your time and support!
Best regards,
Diego