Vivado 2020.2 Block Design Containers

From Partial Reconfiguration, PYNQ v2.7 - #2 by marioruiz

how Vivado generates .hwh file for the IP is probably a question for the Xilinx forum, not PYNQ

But doesn’t the lack of register definitions present a problem for future PYNQ support of BDC’s?
How will PYNQ create a register map for IP in a BDC? This information is not shipped in the HWH. Without it a driver for each core would need to manually created and shipped with PYNQ.

Am I thinking incorrectly about this? Has there been any work done in support of BDC’s I know there was hope to support them. I ask because we are willing to submit PR’s on this, but would like to understand what approaches PYNQ is considering.