Partial Reconfiguration, PYNQ v2.7

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1

Hi all, I am not sure Partial Reconfiguration(dynamic function exchange) is working in v2.7.

  1. I need .hwh file for each partial bitstream. As far as I know, .hwh is generated when I do “generate output products” in Vivado’s block diagram. => I need to use block diagram to get .hwh.

  2. In block diagram, I can’t set a certain IP directly as a Partial Definition in Vivado as mentioned in this tutorial. => I need a hierarchical block for the IP to set is as Partial Definition like below(pr_module being a hierarchical block).
    Screenshot from 2022-01-18 22-13-24

  3. As mentioned in @ggillett 's recent post, there’s no “REGISTERS” in sub-block’s .hwh file. I need something like below in vadd.hwh file to access register A_1, they don’t exist.

<DOCUMENTS/>
  <ADDRESSBLOCKS>
    <ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
      <REGISTERS>
        <REGISTER NAME="A_1">
          <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of A"/>
          <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
          <PROPERTY NAME="SIZE" VALUE="32"/>
          <PROPERTY NAME="ACCESS" VALUE="write-only"/>
          <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
          <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
          <FIELDS>
            <FIELD NAME="A">
              <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of A"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
              <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
              <PROPERTY NAME="READ_ACTION" VALUE=""/>
              <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
              <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
            </FIELD>
          </FIELDS>
        </REGISTER>

I’ve struggled with getting PR working in PYNQ v2.7, but I am not sure it’s possible at the first place.
I can re-produce this tutorial but it doesn’t pass values with registers(LED module exchange).

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2

Hi,

DFX works properly in PYNQ 2.7, the composable overlay uses it.

We can’t really help with the hw design, as it is not PYNQ related.

What have you tried in the software side? If the register map is not populated for the IP in the partial region, you can write your own driver.

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/python_overlay_api.html#creating-ip-drivers

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/overlay_tutorial.html#Creating-a-Driver

Mario

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3

Hi Mario,

Thanks for the input! I will definitely check the composable overlay project.

Just to make sure I understand correctly on your comment on SW modification…

So Vivado(2020.2) doesn’t generate REGISTERS in .hwh for reconfigurable module.
You are suggesting, somehow I need to extract such data from the reconfigurable module IP(in my screenshot above, it’s “vadd”), and write my own driver based on the extracted data? (how Vivado generates .hwh file for the IP is probably a question for the Xilinx forum, not PYNQ support…)

I think another approach could be write my own script to generate .hwh file that contains REGISTERS info.

Thanks!
DJ

1 Like
4

Hi,

You are suggesting, somehow I need to extract such data from the reconfigurable module IP(in my screenshot above, it’s “vadd”), and write my own driver based on the extracted data?

Yes, Vitis HLS already generates a C driver for you with the offset address of the different registers. You can use this. Alternatively, you can work around this adding the registers manually in the python driver. Something like Jenny did here:

how Vivado generates .hwh file for the IP is probably a question for the Xilinx forum, not PYNQ support…

Yes, the Xilinx forums is the right place to ask this question.

Mario

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