I want to make a custom overlay on zcu104. I am using pynq 2.6 and vivado 2020.2. But when I load the bitstream, the .hwh file cannot be parsed properly. The error message is shown as follows.
Can you post an image of the block design? Can you also share the hwh file?
pynq 2.6 has been validated with Vivado 2020.1, so there may be an issue with Vivado versions
The elaborated RTL you provide is difficult to navigate and it is not possible to zoom in enough.
I had a look at the hwh file and it seems that an interrupt controller is not present.
pynq does not support interrupts connected directly to the PS. You need an interrupt controller. Some documentation here
After adding the interrupt controller, I could load the bitstream properly. However, PYNQ cannot find all
the IPs. For example, the axi_dma IP. Does PYNQ support multiple axi_dma IPs? If the answer is yes, what’s could be the reason for only accessing two IPs?
Here only two IPs are addressed. Since I cannot access AXI_DMA IP, I cannot transfer data from PS to PL.
Yes, PYNQ supports multiple DMA
Without seeing the IP Integrator block design and the new hwh file it is difficult to say if something is missing.
You are providing the Elaborated schematics. I’d like to see the IP Integrator block design.
Something like this https://forums.xilinx.com/t5/image/serverpage/image-id/15298i333887E012E58F09?v=v2
Trying to reverse engineer your HWH files it appears you don’t connect the dma engines to the PS so there is no way for PYNQ to interact with them - they’re driven directly by the
DMA_Read_Control blocks. As they’re not in the address space of the PS they won’t appear in the overlay.
I think this reason really makes sense. If it is not practical to modify this design, I guess the only option is to use zynq? Any suggestions are greatly appreciated.