Parse hwh file failed

[Hongduo_Liu]

Hi,
I want to make a custom overlay on zcu104. I am using pynq 2.6 and vivado 2020.2. But when I load the bitstream, the .hwh file cannot be parsed properly. The error message is shown as follows.

[marioruiz]

Hi @Hongduo_Liu,

Can you post an image of the block design? Can you also share the hwh file?

pynq 2.6 has been validated with Vivado 2020.1, so there may be an issue with Vivado versions

Mario

[Hongduo_Liu]

Hi marioruiz,

Please see attached. Regarding the version concern, I will try to use 2020.1 to generate the bitstream and hwh file.
my.hwh (1.1 MB)
schematic.pdf (488.1 KB)

[marioruiz]

The elaborated RTL you provide is difficult to navigate and it is not possible to zoom in enough.

I had a look at the hwh file and it seems that an interrupt controller is not present. pynq does not support interrupts connected directly to the PS. You need an interrupt controller. Some documentation here

https://pynq.readthedocs.io/en/v2.6.1/overlay_design_methodology/pspl_interface.html#interrupt

Zynq PS7 Interrupts

Interrupts are an area that is causing confusing and I’m working on creating some better documentation for them. I’ve also noticed some bugs in the code that can potentially cause spurious interrupt responses that I’m working to fix. In the meantime, I’ve pasted below an example I’m working on in the hope it can be of use to you - just remember it is a work in progress. One thing I will highlight relevant to your example is that we only support interrupts that are ultimately connected to IRQ_F2…

Interrupt error on using two VDMA

PYNQ does not support the interrupts to be connected like that. You need an interrupt controller https://pynq.readthedocs.io/en/v2.6.1/overlay_design_methodology/pspl_interface.html#interrupt Something like this [image] Mario

Mario

[Hongduo_Liu]

After adding the interrupt controller, I could load the bitstream properly. However, PYNQ cannot find all
the IPs. For example, the axi_dma IP. Does PYNQ support multiple axi_dma IPs? If the answer is yes, what’s could be the reason for only accessing two IPs?

[Hongduo_Liu]

Here only two IPs are addressed. Since I cannot access AXI_DMA IP, I cannot transfer data from PS to PL.

[marioruiz]

Yes, PYNQ supports multiple DMA

Without seeing the IP Integrator block design and the new hwh file it is difficult to say if something is missing.

[Hongduo_Liu]

I provide the schematic of the block design and the hwh file for reference. Thank you.design.hwh (1.2 MB)
schematic.pdf (362.9 KB)

[marioruiz]

You are providing the Elaborated schematics. I’d like to see the IP Integrator block design.
Something like this https://forums.xilinx.com/t5/image/serverpage/image-id/15298i333887E012E58F09?v=v2

[PeterOgden]

Trying to reverse engineer your HWH files it appears you don’t connect the dma engines to the PS so there is no way for PYNQ to interact with them - they’re driven directly by the DMA_Read_Control blocks. As they’re not in the address space of the PS they won’t appear in the overlay.

[Hongduo_Liu]

I think this reason really makes sense. If it is not practical to modify this design, I guess the only option is to use zynq? Any suggestions are greatly appreciated.