When I import a multiplication overlay that I wrote, it always return 0

I tried to implement a simple overlay by myself

#include "Multiplication.h"

void multip_2num(int32_t n32In1, int32_t n32In2, int32_t* pn32ResOut)
#pragma HLS INTERFACE s_axilite port=pn32ResOut
#pragma HLS INTERFACE s_axilite port=n32In2
#pragma HLS INTERFACE s_axilite port=n32In1

	*pn32ResOut = n32In1 * n32In2;


This is the final block design.

When I write n32In1 and n32In2 to the address, and then read out pn32ResOut, I find that no matter what the number of writes, the answer is always 0, but n32In1 and n32In2 seems that success was written . And i am sure the address is right.

// control
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of n32In1
//        bit 31~0 - n32In1[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of n32In2
//        bit 31~0 - n32In2[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of pn32ResOut
//        bit 31~0 - pn32ResOut[31:0] (Read)
// 0x24 : Control signal of pn32ResOut
//        bit 0  - pn32ResOut_ap_vld (Read/COR)
//        others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

mul.ipynb (7.4 KB)

I think it’s most likely a ap_control problem multip_2num_0 in block design, I tried writing #pragma HLS INTERFACE ap_ctrl_none port=return into HLS. However, when C/RTL Co-simulation always reports an error, the error message is as follows:

ERROR: [VRFC 10-2989] 'ap_done' is not declared [E:/Program/Fpga/HLS/HLS/lab1/hls_Multiplication/Mul/solution1/sim/verilog/multip_2num.autotb.v:146]
ERROR: [VRFC 10-9491] variable 'AESL_done' is written to by both continuous and procedural assignments [E:/Program/Fpga/HLS/HLS/lab1/hls_Multiplication/Mul/solution1/sim/verilog/multip_2num.autotb.v:146]
ERROR: [VRFC 10-2989] 'ap_done' is not declared [E:/Program/Fpga/HLS/HLS/lab1/hls_Multiplication/Mul/solution1/sim/verilog/multip_2num.autotb.v:147]
ERROR: [VRFC 10-2989] 'ap_done' is not declared [E:/Program/Fpga/HLS/HLS/lab1/hls_Multiplication/Mul/solution1/sim/verilog/multip_2num.autotb.v:175]
ERROR: [VRFC 10-8530] module 'apatb_multip_2num_top' is ignored due to previous errors [E:/Program/Fpga/HLS/HLS/lab1/hls_Multiplication/Mul/solution1/sim/verilog/multip_2num.autotb.v:29]
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/multip_2num/xsimk.exe" does not exist 
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***

I tried searching online and reading documents such as ug1399, but the problem was still not solved.
My vitis and vivado version is 2022.2, the board i use is kv260, the PYNQ version is 2.7

Sorry for being lengthy.
Hope anyone can help me figure out what I missed.

Hi @NvCenter,

Your IP is never started because you left the ap_ctrl unconnected in your IP Integrator.
The best solution is that you map the return of your HLS function the the AXI4-Lite port, then you can control the IP from PYNQ.

#pragma HLS INTERFACE s_axilite port=return


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Hi Mario,
Thank you very much! It works. By the way, can you recommend me some resources on this?

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Hi @NvCenter,

All the information is on the Vitis-HLS User guide