I’m working with the RFSoc 4x2 board and my design is originally based on RFSoc_qsfp_offload exemple. I’m trying to set the lmk and lmx frequencies to 500.0 MHz. The reference clock to the ADCs and DACs are set to 500 MHz. However, when I call the method set_rf_clks(lmk=500.0,lmx=500.0), the ADCs and DACs get stuck in state 14 ( and thus can’t be used) whereas if I set the lmk and lmx to 245.76 and 491.52 MHz (with the reference clocks at 500 MHz), what is the case in the original design , the ADCs and DACs are in a good state ( state 15,enabled,…). I’m confused why this is the case and I would appreciate any help for fixing this.
Thanks in advance,
I have a couple of questions for you.
- Did you generate your 500 MHz LMX and LMK clock files using TICS PRO?
- Is there are particular reason why you need the LMK and the LMX at the same frequency? Was this a design choice?
Sorry for the late answer. I haven’t generated the files using TICS Pro, they were by default present in the xrfclk folder on pynq.
Concerning the LMK and LMX at the same frequency, yes this is a design choice.
But now, I can initialise the clocks to 500.0 MHz without any problem. The only issue is that, I am also trying to implement Multi tile synchronisation, I have implemented it on vivado and on pynq and it runs without any problems (on pynq I’m using similar methods as “init_tiles_synch” and “synch_tiles” as in RFSoC-MTS/rfsoc_mts/mts.py at main · Xilinx/RFSoC-MTS · GitHub).
However, the methods run well but the signal received are still not synchronized. Would you have any idea how it can run correctly on pynq but still receiving signals not synchronized?
Thanks for your help,