No, I do not have the script. But, you do not need one. Use the same image you are feeding from the notebook, perhaps you want to use a smaller image that can be fully captured by the ILA.
Mario
Hi @pedropinheiro2, i have not used it yet. I’ll try this week.
@marioruiz thanks for the reply, but how should i “use the same image”? In python is just sending an array as parameter, what about Vivado IP integrator and its debugging environment shown in the video?
From where? VHDL testbench or such?
I have never used ILA before.
You do not need a test bench to use the ILA. The ILA also referred as ChipScope is hardware built in your design that allows you to capture the internal signal that are happening in your design.
So, you download the overlay, configure the triggers in the ILA and run the notebook. Then you can observe what the ILA has captured.
Mario
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Hi @marioruiz,
I believe I found the solution. The TKEEP and TSTRB sidebands from the output stream were always 0 and then the corresponding byte was always null and could safely be ignored.
From https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Meaning-of-AXI-Stream-side-channel-signals/td-p/1118259, I realized that the DMA needed those sidebands equal to 1 and I’ve changed my HLS code, introducing the following lines
axis pix_out_sidebands;
pix_out_sidebands.data = pix_out;
pix_out_sidebands.keep = 1;
pix_out_sidebands.strb = 1;
pix_out_sidebands.last = ((i==height-1) && (j==width-1)) ? 1 : 0;
dst << pix_out_sidebands;
Now, the DMA does not stall anymore.
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That’s fantastic. 
In your case tkeep is only one bit, more generally you will set up keep = -1, so all bits are 1.