Hi!
I have a zcu208 design based on the example GitHub - Xilinx/RFSoC-MTS: A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS). in which I use four ADCs. Specifically I use ADC0, ADC1, ADC2 and ADC3. To check that the alignment between them is correct, I feed the same signal into ADC0 (Tile0) and ADC2 (Tile1), acquire a time window and then calculate the phase difference between both ADCs. I repeat this process for many acquisitions. As a result, one would expect that, if they are correctly aligned, the phase difference will be approximately the same value in all acquisitions, and this is true in most cases. However, sporadically, some acquisitions show a noticeably different phase difference. In Vivado I have implemented the same clock tree as in the example, with the difference that in my design the sampling frequency is 4900 MHz, pl_clk 612.5MHz and pl_sysref 8.75MHz. The external clocks LMK and LMX have been configured correctly from pynq to achieve the necessary frequencies.
My question is: Is it possible that the system loses the synchronisation between Tiles and resynchronises automatically? On the other hand, document PG269 describes the steps to follow to achieve synchronisation between tiles. Specifically, step 5 indicates that a synchronisation of the digital features (mixer, etc.) has to be performed. How is this step performed with the mts_rfsoc package?
Thank you very much for your help
David.
Can you provide any screenshots demonstrating the issue you’re experiencing? I might be having similar issues, but I’m not sure. What I see appears as a discontinuity, but that in turn has the effect of moving tiles out of phase of each other.
Generally speaking, my design consists of four channels, each with a 512-band ADC + channelizer, which returns complex (I, Q) values. Therefore, an acquisition involves obtaining a frequency spectrum of the input signal.
In my tests, I used the same input tone for all four channels. I subsequently performed 200 acquisitions and focused on the I, Q values obtained for band 100 to calculate the phase. It’s worth noting that I selected band 100 because the input tone frequency corresponds to that band.
When subtracting the phase between two synchronized ADCs, the phase difference is expected to be very small, as it will never be 0 due to noise and small differences in the RF circuitry.
The following graph shows the phase difference between ADC0 and ADC1 obtained for the 200 acquisitions. These ADCs are synchronized by default because they belong to the same Tile 224. You can see that the phase difference remains very small across all acquisitions, as expected.
On the other hand, I calculated the phase difference between ADC0 and ADC2, which belong to different Tiles (Tile 224 and 225, respectively). Therefore, multi-tile synchronization is necessary to obtain results similar to the previous case. However, discontinuities appear (see the figure below).
I notice that the xrfdc library I use in PYNQ supports LogiCore version 2.4, but my hardware design uses version 2.6.
Could this be the problem?
That’s possible, and I’ll try to look into that myself as well later, but for now I want to show a screenshot from my end that might be a different view of the same problem:
Looking in the time domain (910 MHz source, 900 MHz I/Q mixer, 20x decimation), we can see these discontinuities that are basically synchronized for the same tiles, but are different for different tiles. My current solution to get around this is to avoid mixing and then synthesize I/Q in python with scipy.signal.hilbert(), but that’s a significant efficiency loss. If it’s not too hard to change your view of the data, it would be interesting to see if you have the same issue in the time domain.
