Hi!
I have a zcu208 design based on the example GitHub - Xilinx/RFSoC-MTS: A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS). in which I use four ADCs. Specifically I use ADC0, ADC1, ADC2 and ADC3. To check that the alignment between them is correct, I feed the same signal into ADC0 (Tile0) and ADC2 (Tile1), acquire a time window and then calculate the phase difference between both ADCs. I repeat this process for many acquisitions. As a result, one would expect that, if they are correctly aligned, the phase difference will be approximately the same value in all acquisitions, and this is true in most cases. However, sporadically, some acquisitions show a noticeably different phase difference. In Vivado I have implemented the same clock tree as in the example, with the difference that in my design the sampling frequency is 4900 MHz, pl_clk 612.5MHz and pl_sysref 8.75MHz. The external clocks LMK and LMX have been configured correctly from pynq to achieve the necessary frequencies.
My question is: Is it possible that the system loses the synchronisation between Tiles and resynchronises automatically? On the other hand, document PG269 describes the steps to follow to achieve synchronisation between tiles. Specifically, step 5 indicates that a synchronisation of the digital features (mixer, etc.) has to be performed. How is this step performed with the mts_rfsoc package?
Thank you very much for your help
David.