Is there any bare metal implementation available? Or any way to control the ADC directly with code (a script) rather than using a GUI?
I plan on using my own modules on the PL to process Rx signals. Where in the HDL design can I tap in to receive them?
You can use PYNQ (Python) on the command line or from a Python script to control the ADCs instead of using Jupyter notebook. (I assume by GUI you mean Jupyter).
You can find source code for the Vivado designs used with PYNQ here:
You don’t have to use PYNQ with these designs.
You can instantiate the RFSoC Data converter IP in your own design. This is the interface block to control the ADCs.
It is a complex block and needs to be configured via the AXI slave interface, so you can’t just connect some HDL signals. This is a great example of why you might want to use PYNQ - it make config and control of the ADCs a lot easier.
Thank you for your quick answer Cathal,
Yes, when I wrote GUI I was thinking about the frequency planner interface but actually meant other ways to control the ADCs other than Jupyter. Is it possible for the system to automatically run a configuration script on startup? I haven’t read the sources yet and I’ve never used a PYNQ device before.
I have no problem on configuring the ADCs via PYNQ, but I do need the ADC’s Rx signals available on the PL to do some custom processing. I’ll read the PG269 now, but before I do so am I correct to assume I can get those signals from that IP?
@cathalmccabe any info on this?
Yes, you could run something automatically on startup.
This is a simple way to run something on boot:
Thanks once more @cathalmccabe ,
If I modify the HDL design do I have to build the PYNQ image following this procedure? Or is there another way? I do not intend to modify the software part yet.
Also is there any way to do everything on Windows?
Lastly, it seems I need a Vivado license to work with this board. Can you confirm this?
No, the PYNQ image doesn’t need to be modified. If you want to change the hardware, you do this in Vivado, and used the new design with the PYNQ image.
Yes, you need a Vivado license to build designs for the RFSoC part on this board.
Oh okay, I’m guessing one could SSH into the board and copy the bit, tcl and hwh files there then.
In which cases would I want to modify the image? Or it isn’t necessary for common designs?
Yes, ssh etc. can be used. You can also upload directly via your web browser with Jupyter Notbeook/Lab.
You can install new software packages (apt-get install, pip install etc.) and copy new files or software to the PYNQ image, but you don’t need to rebuild or “modify” the image.
@cathalmccabe : when one configures the RFSoC Data converter IP via Vivado, is that enough to make the ADCs run with that initial config or is additional software intervention necessary?