Hi,
In this example GitHub - Xilinx/PYNQ-HelloWorld: This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework., the authors show us how to use resize kernel with some Python code, but it needs a DMA and some AXI4-Stream4 Data Width Converter to transfer data.
I wonder is there a way to use resize kernel directly without DMA? And how can we do it?
Thank you in advance.
I am investigating a resize example with Vitis flow. It does not use DMA. Since OpenCL handles data transaction in this approach, I still have no idea how data stream is fetch into and get from resize kernel.
DMA is used to stream data to/from the IP, not to control the IP.
The control is done through the AXI slave port.
You can modify the HLS code to read directly from PS DRAM (where the image data is stored). This would involved switching the AXI stream interfaces to AXI masters.
You could also modify the code or create your own design with the the data width converter removed and functionality built in to your IP.
Cathal
Thank you for the quick suggestion.
I edited the question for more clear.
I see the example HLS code from Vitis Library itself read directly from PS DRAM.
But I still don’t know how to achieve that on PYNQ framework.
Looked into the overlay tutorial that they use DMA, and the read/write methods in pynq.overlay are based on offset address.
https://pynq.readthedocs.io/en/v2.7.0/overlay_design_methodology/overlay_tutorial.html
https://pynq.readthedocs.io/en/v2.7.0/pynq_package/pynq.overlay.html
What am I missing?
I’ve just added this tutorial on using HLS IP with AXI Master interfaces from PYNQ which should answer your questions.
Cathal
Thank you very much. Since the tutorial is clearly answering my concern, I’m studying it.
