I have a task on hand where in I take stream data on PS in one Ethernet interface (Eth0), do some processing in PL (HLS AXI stream IP) and return the processed data to PS , then send it over to another network on Eth1 interface. But the Eth1 seems disabled on PS, as when a network cable is attached to this port, there are no auto negotiation lights glowing here. Is this only accessible on PL. How to make it accessible to PS side. Does this process require building own custom PYNQ image.
This question is outside the scope of the PYNQ forums. You may be better off reaching out to Aldec or checking the schematics user manual of this board.
If the eth1 interface is not enabled in the current image, this would likely involve re-building the image and probably adding hardware on the PL.
Hi!
This is a known issue related to device tree overlay. Kernel can not communicate to PHY during boot up. MDIO connections are available after loading programmable logic from base overlay. Can you replace boot partition files with files from the attached zip?
The package contains BOOT.BIN with disabled eth1 by default and base.dtbo file which triggers system to load kernel driver for eth1 when an overlay is loaded. In PYNQ a user should load an overlay with dtbo parameter e.g.:
ol = BaseOverlay("base.bit", dtbo="/home/xilinx/base.dtbo")
