Access to PHY module (Ethernet port) with PL

Hello !
I have project where I have to work with Ethernet frame only with a FPGA (PL part). It is possible to use PHY module (MIO) with PL part? Or it is possible to redirect MIO PHY (ethernet) ports throughout EMIO port?

I have already researched in the documentation and for me it’s not possible.

PhY(Ethernet) is connected to MIO port and PL is connected to EMIO port. I found this in the document ug585-Zynq-7000-TRM.pdf

Thank you ! :jigsaw:

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You can’t do what you are asking the EMIO (FPGA logic, PL pins) can be used to connect to the PS Ethernet MAC, but this isn’t want you want to do.

This may be of interest, but it routes the Ethernet frames to the PL via the PS. It was last updated for PYNQ v2.4 and you can see some modifications to the image were needed.

Depending on the board you are using, you could have a new Ethernet interface connected to the PL if you want to process Ethernet frames in PL.




The overlay written by Xilinx is quite neat, but for my use purpose (which is similar to axelm), I want to be able to communicate with the FPGA pins directly. Is there a way to not use this overlay and directly make the ethernet talk to the PL, and have no use of PS or linux OS.

xilinx - Direct Access to Ethernet port via FPGA on Pynq-z2 board - Electrical Engineering Stack Exchange

The simple answer is “no” you can’t do this with the PYNQ-Z2. If my previous answer wasn’t clear, the Ethernet is connected to the MIO pins which are connected to the PS.

If you want an Ethernet connection directly to the FPGA pins, you could add an additional Ethernet interface to PL pins. For example: Pmod NIC100: Network Interface Controller - Digilent

However, the Pmod pins are not high speed, so I don’t know what speeds you would be able to achieve with this. (By the way, I haven’t used this Pmod. I don’t know how well it would work on the PYNQ-Z2).

If you want a high speed network interface direct to FPGA pins, you probably want to use a different board.


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What you have stated is quite clear and has solved my query. I also think that using ethernet via the pmod pins on pynq is not a good idea. Since the upper level protocols of the ethernet are highly algorithmic and processing intensive, it is best handled by the processor. The data can be relayed from the processor to the FPGA by the pynq-networking overlay code.


Just a note about this networking overlay.

The overlay only works with v2.4 pynq image and does not work with v2.5 and v2.6 due to some compilation and reference errors.

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