I have project where I have to work with Ethernet frame only with a FPGA (PL part). It is possible to use PHY module (MIO) with PL part? Or it is possible to redirect MIO PHY (ethernet) ports throughout EMIO port?
I have already researched in the documentation and for me it’s not possible.
The overlay written by Xilinx is quite neat, but for my use purpose (which is similar to axelm), I want to be able to communicate with the FPGA pins directly. Is there a way to not use this overlay and directly make the ethernet talk to the PL, and have no use of PS or linux OS.
However, the Pmod pins are not high speed, so I don’t know what speeds you would be able to achieve with this. (By the way, I haven’t used this Pmod. I don’t know how well it would work on the PYNQ-Z2).
If you want a high speed network interface direct to FPGA pins, you probably want to use a different board.
What you have stated is quite clear and has solved my query. I also think that using ethernet via the pmod pins on pynq is not a good idea. Since the upper level protocols of the ethernet are highly algorithmic and processing intensive, it is best handled by the processor. The data can be relayed from the processor to the FPGA by the pynq-networking overlay code.