Added IP before HDMI out IP not working

[marioruiz]

Hi,

You should be using Vitis HLS 2020.2 to match the Vivado version as well as using hls:stream.

You should also verify that your HLS IP is achieving an II=1. Otherwise, you will not get an output.

There a two part tutorial on DMA here

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

How is it with the data types? I tried that and had an issue due to the data type of the PynqBuffer being always uint8 (see here).

You are using PIXEL_RGB in that case, so you will get three channels per pixel 8-bit each that’s why you se uint8

Mario