PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Custom Video Pipeline Overlay for ZCU104 Issue

I have built custom HLS video processing cores for the Z1 and was successful in building a custom overlay that worked as expected with the hdmi in and out tie. I took this same core and changed it from 24 bit to 48 bit to target the ZCU104 (changing the referenced board part accordingly). I also placed the core in-between the color_convert and pixel_pack cores as I did in the Z1. After rebuilding the bitstream I then added the 3 custom system files to my PYNQ SD card (custom.bit, custom.hwh, custom.tcl). Using the Overlay class my script successfully loads the new overlay but when I run the following code to configure the hdmi I got an errror:

Is there something obvious that I’m missing?

The video pipeline for the ZCU104 needs some extra setup that is handled in the _init_clocks function in base.py. I would recommend creating your own overlay class and adding the _init_clocks and download functions into it.

Peter

@PeterOgden thanks for the suggestion. Since my last post I have changed three things to ensure I hadn’t made a simple error:

  1. I changed my HLS core to perform a simple passthrough function on the video stream so as to be a sanity check.
  2. Per the instructions in the Pynq Manual (https://buildmedia.readthedocs.org/media/pdf/pynq/v2.3/pynq.pdf) at the top of page 78 “It is usually appropriate to insert the IP after the pixel_pack block on the HDMI-In block, or before the pixel_unpack
    block on the HDMI-Out side.” – I converted my HLS core to be 64 bit and placed it after the Pixel Pack in the HDMI-In block.
  3. I built this new system and named the .bit, .tcl and .hwh files base and placed them in the sd card directory where the original base files where.

Now, the system allows me to run the jupyter notebook for hdmi_introduction that does the basic hdmi tie-in. I get a video feed but the output looks like perhaps pixels are being skipped. I get series of vertical BGR lines intermixed with actual footage (see attached image).

I’ve attached my hls code as well and an image of the block diagram in Vivado.

Any suggestions?