Ap_uint<1> matrix

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1

Hi all,

I’m having another issue with my design. This is the top function that is synthesized.

void MatrixVectorActivation_0(
                    hls::stream<ap_uint<64>> &in0,
                    hls::stream<ap_uint<512>> &weights,
                    hls::stream<ap_uint<64>> &out,
                    ap_uint<1> is_input_faulty,
                    ap_uint<1> is_weight_faulty,
                    ap_uint<3> bit_faulty,
                    ap_uint<1> mac_faulty[8][8]
                    )

Everything is connected correctly in Vivado, since in the bitfile I can see all things. In addition, these are the generated address in the verilog file:

//------------------------Address Info-------------------
// 0x00 : Control signals
//        bit 0  - ap_start (Read/Write/COH)
//        bit 1  - ap_done (Read/COR)
//        bit 2  - ap_idle (Read)
//        bit 3  - ap_ready (Read/COR)
//        bit 7  - auto_restart (Read/Write)
//        bit 9  - interrupt (Read)
//        others - reserved
// 0x04 : Global Interrupt Enable Register
//        bit 0  - Global Interrupt Enable (Read/Write)
//        others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
//        bit 0 - enable ap_done interrupt (Read/Write)
//        bit 1 - enable ap_ready interrupt (Read/Write)
//        others - reserved
// 0x0c : IP Interrupt Status Register (Read/COR)
//        bit 0 - ap_done (Read/COR)
//        bit 1 - ap_ready (Read/COR)
//        others - reserved
// 0x10 : Data signal of is_input_faulty
//        bit 0  - is_input_faulty[0] (Read/Write)
//        others - reserved
// 0x14 : reserved
// 0x18 : Data signal of is_weight_faulty
//        bit 0  - is_weight_faulty[0] (Read/Write)
//        others - reserved
// 0x1c : reserved
// 0x20 : Data signal of bit_faulty
//        bit 2~0 - bit_faulty[2:0] (Read/Write)
//        others  - reserved
// 0x24 : reserved
// 0x40 ~
// 0x7f : Memory 'mac_faulty' (64 * 1b)
//        Word n : bit [ 0: 0] - mac_faulty[4n]
//                 bit [ 8: 8] - mac_faulty[4n+1]
//                 bit [16:16] - mac_faulty[4n+2]
//                 bit [24:24] - mac_faulty[4n+3]
//                 others      - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

Right now my issue is to be able to write the values of mac_faulty from the python host. I’m able to set the value of the other axilite parameters, but I don’t know how to manage the mac_faulty parameters.

Do you have any example or can you provide some help?

Thanks
Giovanni

P.S: After I fix everything I plan to write a tutorial and post it here, there are issue I faced that can be interesting to explain to others.

2

I apparently fixed the problem. The verilog file is a bit misleading. In fact the starting address for the mac_faulty is not 0x7f but 0x40, where there is the ~.

3

Agree - as there are some problems in the comments written… Where it lists “Word n: bit [0:0]” is also inaccurate. and does not reflect your 2D array. Your mac_faulty memory is mapped to address range 0x40 ~ 0x7f but it seems each 1 bit element was mapped to its on row. You may want to investigate the AGGREGATE pragma to make this compact. Alternatively, if you re-map using the ap_uint<8> for each row you can control best how the 2D array is unwound to the address map.

Regards,
-N

2 Likes
4

Thanks for the suggestions. I will have a look at the AGGREGATE pragma. Unluckily I cannot change the type, because I’m really short on resources, and I noticed that using ap_uint<8> consumes a little more hardware resources compared to a matrix of ap_uint<1>.