When I used custom

[cydiazero]

Hello, I have problem…
I use Pynq-z2 board is installed v3.0.1 image and my Vivado version is 2024.1
I want use my custom accelerator that was written by Verilog HDL.
So, I tried a tutorial of Verilog Module Overlay. I referred a post, “Tutorial: Creating a new Verilog Module Overlay”
But, I have a problem when I use Overlay.my_verilog_custom_ip.write function.
When I use that function, the Jupyter notebook is looping (“[*]”) and notify connection failed few second later… The read function is work.
So, I tried using MIMO module. But It is not solution.

(I modify 0x0C. That is my intention.)

How to solve this problem?

Thank you.

[mtsanic]

Hi @cydiazero ,

Are you sure your IP is memory mapped?

Best

[cydiazero]

Hello @mtsanic , Thank you for your interest in my question.
But, I don’t understand “your IP is memory mapped?”
Are you asking me “Modify AXI Interface” or “Set IP Register in tab of Addressing and Memory”?
I applied both.

I modify a AXI Interface of my IP.
In my code, I added my module “adder”.

and I modify the section of AXI write channel.

There was no word in that tutorial, I added the infomations of four registers in Addressing and Memory section.

Thank you!

[cydiazero]

I found solution.
The problem is vivado 2024.1.
When I try vivado 2022.2, It is working!!