Array Transfer using Axis keeps waiting

Support
1

Hello. I am new to pynq. Trying to transfer arrays between PS and PL on Pynq-z1 board.

The program is a small neural network. I am imitating the writing from an online tutotial:
https://bitbucket.org/akhodamoradi/pynq_interface/wiki/AXI_DMA_2

For my case, the function input is a (13,) shape float array. The output is a (2,) shape float array. Basically, it is a small neural network input and output.
The neural network is generated from the tool called ‘hls4ml’ that converts a keras model into hls code.
The generated code uses ap_fixed as input and output and I am trying to send data as float arrays and then convert to ap_fixed for generated code to run.
So now I have passed simulation, generated ip and bit file. From the notebook file, seems that it stucks its asterisk at dma output receiving step:
dma_out.recvchannel.transfer(out_buffer)
dma_out.recvchannel.wait()

Wondering if it has anything to do with the data type conversion or some other reason?
I have attached the program files and block design.
Thank you!

fec_latclass_mlp2_axispynq.zip (415.8 KB)

2

What about running the program in the following order:

def run_kernel():
    dma.sendchannel.transfer(in_buffer)
    dma.recvchannel.transfer(out_buffer)    
    resizer.write(0x00,0x81) # start
    dma.sendchannel.wait()
    dma.recvchannel.wait()

This is proved to be working for our examples here:
https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/boards/Pynq-Z1/resizer/notebooks/resizer_PL.ipynb

Also, I noticed that you instantiated the in and out buffers using np.float32. I am not sure about its impact because I have not done such a design in the past. Maybe safer to do integers?

3

Dear @rock, could you please explain what this mean and how to get those address?

resizer.write(0x00,0x81) # start

I would like to use for my own IP to get the result from data processing, but it failed.

dma.sendchannel.transfer(in_buffer)
dma.recvchannel.transfer(out_buffer)    
**custom_ip.write(in_buffer,out_buffer) # start**
dma.sendchannel.wait()
dma.recvchannel.wait()

I made something like this. is that correct?
thanks

4

That is usually needed when an IP requires a start signal. For your HLS IP, if you check the program comment generated by Vivado, you could find some register information about the generated IP. This is not required if you use your customized RTL IP.

5

Hi @rock Thank you for your answer, you are right.
I am still curious about:

As I checked the memory address:

but where is 0x81 from?

Thank you

6

0x81 = 10000001 in binary (bits 0 and 7 are set to 1. This will set ap_start, and auto_restart:

Cathal

7

Dear @cathalmccabe thank you very much, appreciate it. I totally understand now.