PYNQ: PYTHON PRODUCTIVITY

AXI BRAM breaks overlay design

Hello,

I’m trying to get a rather simple block design to work on Vivado 2019.1 (Linux). I’m using the PYNQ-Z2 with the v2.5 boot image.

It’s just a Zynq7 PS, three GPIOs, an AXI BRAM controller, and what gets added by the connection automation (reset, AXI SmartConnect, memory generator).

Without the BRAM, the project works fine. But with the BRAM, it fails in the synthesis step.

The generated error is:
“design1_axi_bram_ctrl_0_bram_0_synth_1 (1 error)
[Common 17-55] ‘set_property’ expects at least one object.
Resolution: If [get_(value)] was used to populate the object, check to make sure this command returns at least one valid object.”

There is also one critical warning, in case it is important:
“design1_axi_smc_0_synth_1 (1 critical warning)
[Common 17-161] Invalid option value ‘10,000’ specified for ‘period’. [”~/Xilinx/Vivado/2019.1/ram2/ram2.srcs/sources_1/bd/ram_desu/ip/ram_desu_axi_smc_0/ooc.xdc":3]"

Do you have an idea what might be the cause of this problem?

Regards,

Frank

p.s.
For more details, I’ve been following this tutorial:

Please share your .tcl file. This is a Vivado issue, not PYNQ-related.
There’s probably an error in your tcl

I also recommend you redirect this question to the Xilinx forum (or search for it there) because again, this is a Vivado issue (or likely a mistake in your project)

For instance, take a look here: https://forums.xilinx.com/t5/Synthesis/set-property-expects-at-least-one-object/td-p/818063

Thank you, I have tracked the problem down!

It was a problem with my localisation settings. Some parts of Vivado honour the decimal separator setting, some parts don’t and expect a decimal “.” dot. That results in Vivado confusing itself. I fixed those settings, and now it works.

Regards, Frank

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