I am currently developing a Pynq project, using a Pynq-Z2. I have already followed the tuorials and successfully created and used bitstreams from Python using the leds and switches. I have put together an audio IP block (which at present just passes audio through from line in to headphones). It wor…

Instantiating the Overlay will do things like read meta info about the design, which will set PL clocks. I wonder if the clocks are not being set properly. Have you constrained the clocks in your design properly? I’m assuming each time you load with JTAG that this is after a PYNQ image has booted? …

Thanks Cathal. I wondered about clocks too. The current design just uses, externally, a separate 100MHz clock tied to a pin, and the following constraints; there is also a 48MHz clock generated from it then divided by 2 for the master clock snet to the Audio Codec. create_clock -period 10.000 -na…

You mention that instantiating the overlay sets PL clocks. I’ve looked through the documentation, but I cannot find anywhere a full statement of exactly what does happen, and that as a result, you should or should not do various things in your own bitstreams. Does that documentation exist? If it do…

What is your clock_100 connected to? If you are using the PL “Ethernet” clock, this clock is unstable unless an Ethernet cable is plugging in. If you are using PYNQ this should be OK - assuming you have the cable plugged in. For reference, the boot jumper determines the boot source for the board […

Thanks gnatale - but that link says that Pynq should set the clocks up as per the overlay’s request. So this implies that I dont have to take care of anything, and that the necessary info will be acquired from the tcl, or hwh, file. “The PL clocks can be programmed at runtime to match the requireme…

Thanks again Cathal, As the extract from my constraint file shows, clk_100 is connected to pin H16. Whenever I have tried this, Ethernet has been plugged in, so that’s not an issue. As I said (implictly) above, I also tried using FCLK_CLK0, which Pynq reports as running at 100MHz, but that did not …

Well, here is an unhelpful but maybe informative data point. Previously, the clk_100 port was just marked as a regular port in the IP Packager. I changed it to be marked as a Clock port. After doing that, loading the overlay with audio_controller = Overlay("new.bit"); completely locks up Pynq -…

I struggled with clocking in my first project, which was a frequency counter. The clk_100 input to your block definitely needs to be connected to the PS clock (FCLK_CLK0). You’ll need this later for AXI to work. Now you need a clock for whatever is to the left of the diagram you shared. I think …

Steve thanks for your comments. I’ve already tried an alternative to the one in my block diagram with clk_100 connected to FCLK_CLK0, but that gave just the same outcome - worked as a standalone bitstream, not when loaded from Pynq. The only way I’ll be using AXI in future is to send parameters t…

Bitstream works ok when programmed by JTAG but not from Pynq

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cathalmccabe January 17, 2020, 10:30am 11

At this stage I’d chipscope the IP to check the signals coming in and going out.

Can you share the design?

Cathal

External ADC does not work in PYNQ but it works if loading the bitstream in Vivado

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Bitstream works ok when programmed by JTAG but not from Pynq

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