Hello there,
I’m using an ADC board (Alinx FL9613) connected via FMC LPC connector to a ZCU104 board. I’ve been using the code provided by Alinx to simply program my ZCU104 via USB in Vivado. I only changed the PLL to provide 250 MHz instead of 50 MHz, and I added an ILA to monitor the different channels, and the status of the clock chip on the board. I also changed the constraint to adapt it to the ZCU104. The bitstream loads fine, and the design works. The clock chip locks, and the waveforms show up correctly. These are the debug files in the zip below.
I then decided to create an IP containing this code that has both an AXI lite slave port and an AXI stream master port.
I created then a block diagram with this IP, generated the bitstream, I then load the overlay, and, no matter what I do, the clock chip on the ADC board (an AD9518 never locks). In fact, the full 1F register that contains the lock information is all zero (when loading the bitstream via USB it has a value of 4f), which means the VCO calibration never finishes, it is not above the threshold, the reference is not above the threshold, and the PLL is not locked. If you open the code you can see that the AD9518 lock bit is what prevents the ADC to be setup, so I haven’t tried even reading the ADC output. The IP files, tcl and block diagram are in the zip below. I couldn’t upload all the files as they were above the 10 MB limit.
I spent more than the past 2 weeks trying to figure this out and nothing I do seems to solve this issue… Some of the things I tried are:
- Move the clock wizard outside the IP I generate
- Drive the clock wizard with a 300 MHz coming from the Zynq Ultrascale block instead of the outside pins I was using
- Using directly 250 MHz coming from the Zynq Ultrascale block (this is what I’m currently using)
- I currently use the slave register I had designated for the ADC channel selection to reset the clock chip, but it doesn’t work anyway resetting him
- I added more ILAs to look “under the hood” and while resetting I checked the waveforms during setup and it seems the SPI registers gets set-up appropriately
I even tried to get the clock output from the AD9518 and there is a clock at the output at the right frequency, I think sometimes it glitches because I compared it to the clock coming from the Zynq block and sometimes they are synchronized, sometimes they are out of phase (see attached figures).
I am assuming the error is in how PYNQ initializes some stuff, I am excluding hardware issues since I checked the constraint multiple times, and it does work with the Vivado bitstream, it just never works when using an overlay. Or maybe the way the wrapper is putting everything together.
Any suggestions are welcome. If you need any other file or want me to generate any waveform please let me know.
Kind regards
ADC IP and PYNQ files.zip (198.6 KB)
ADC debug files.zip (57.6 KB)
P.S.: I saw this other forum post Bitstream works ok when programmed by JTAG but not from Pynq - Support - PYNQ and tried running “sudo systemctl disable boot_leds” as suggested there but the terminal says “Failed to disable unit: Unit file boot_leds.service does not exist.”
I have currently a counter to show at the AXI stream master, this was me just testing the DMA part of the code, fell free to ignore it. There is also an IP that reinterprets the raw ADC data in Fix_16_14 to get the value in Volts (generated in Vitis Model Composer). I think these are irrelevant with my issue.