I confirm that this is true. I observed it on my PYNQ-Z2 board, where the 125MHz clock generated by the Ethernet PHY chip is fed as a global clock input to the PL. This clock becomes unstable when no Ethernet PHY connection is established.
Regards
I confirm that this is true. I observed it on my PYNQ-Z2 board, where the 125MHz clock generated by the Ethernet PHY chip is fed as a global clock input to the PL. This clock becomes unstable when no Ethernet PHY connection is established.
Regards