Simple VHDL project on PYNQ-Z2

Hi everyone, I want to purchase the PYNQ-z2 board. But before purchasing it, I have checked on the internet if it’s the best solution for my need.
Unfortunately, I didn’t find a simple answer to my question.
Here are my questions:
I want to understand some basic information that was missing from me when searching on the internet:

  1. I saw that every example runs on the board designed with the VIVADO IP CATALOG. But if I want to create my VHD file from scratch and upload it to the board, are there some limitations?

  2. If I want to upload the bitstream file to the board, the only way to do so is by using the Jupyter notebook? or it can be done directly from VIVADO “open hardware manager >> program device.”?

Thanks in advanced. :smiley:

Regarding your questions:
Ad. 1
I encountered a limitation of the PYNQ-Z2 board, which is that the clock signal applied to the PL (pin H16) is unstable in certain situations.
In particular, this applies to situations in which we do not use PS at all in the FPGA design.
Take a look at the discussion in the indicated link:

The solution (quite troublesome) in this case is to add the SDK / Vitis project to the Vivado project (even if we do not need to use PS) only to initiate correctly generated clock signals for PL in PS.

Ad. 2
You can easily upload the project to FPGA using the JTAG built into the PYNQ-Z2 board - via USB.
So, as you wrote “it can be done directly from VIVADO” open hardware manager >> program device. "


hello, I viewed this video from Diligent, and I think it can be helpful for you

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