Simple VHDL project on PYNQ-Z2

[AndrzejP]

Hi.
Regarding your questions:
Ad. 1
I encountered a limitation of the PYNQ-Z2 board, which is that the clock signal applied to the PL (pin H16) is unstable in certain situations.
In particular, this applies to situations in which we do not use PS at all in the FPGA design.
Take a look at the discussion in the indicated link:

Bitstream works ok when programmed by JTAG but not from Pynq

I confirm that this is true. I observed it on my PYNQ-Z2 board, where the 125MHz clock generated by the Ethernet PHY chip is fed as a global clock input to the PL. This clock becomes unstable when no Ethernet PHY connection is established. Regards

The solution (quite troublesome) in this case is to add the SDK / Vitis project to the Vivado project (even if we do not need to use PS) only to initiate correctly generated clock signals for PL in PS.

Ad. 2
You can easily upload the project to FPGA using the JTAG built into the PYNQ-Z2 board - via USB.
So, as you wrote “it can be done directly from VIVADO” open hardware manager >> program device. "