BRAM access by HLS IP and PYNQ

[Willy]

PYNQ version: 2.7
Hi all,
I’m trying to do the exercise about the BRAM.

1. Create HLS IP which copy the data of A array (m_axi) to B array (located in BRAM)
   
2. Create Vivado project and add above IP with BRAM generator and controller (for PS CPU access)
   Block design:
   
   
   
   Address Editor:
   
   
3. Create Python code on PYNQ-Z2 and process following steps:
   (1) Instance IPs (read_romcode_0 and axi_bram_ctrl_0)
   (2) Allocate input_buffer and initial it with test pattern
   (3) Use IP axi_bram_ctrl_0 mmio function (write, read) to initial BRAM.
   (4) Configure IP read_romcode_0 source address (input_buffer), and trigger ap_start (offset 0x00[0] = 1)
   (5) Use IP axi_bram_ctrl_0 mmio read to check the context of BRAM after read_romcode_0 move the data.
   
   

In my expected, the result should be the same in the step 2 and 5. (read_romcode_0 move the input_buffer data into BRAM).
But the result is strange, the IP seems move the data with a different start base. (I suppose they should use the base 0). Does any one can help to answer? thanks!!

[cathalmccabe]

I don’t see anything obvious wrong. I see you have marked some of the interfaces for debug. I’ve suggest you check these interfaces to get a better idea about what is happening.
There are a few different things that could be happening that are masked if you can only see the final output.
For example, it looks like 0xcd0 is being written to address zero. The writes may start correctly at address zero, but then loop back to 0x0 for some reason. Checking the transactions should make the issue more obvious.

Cathal

[Willy]

@cathalmccabe Thanks for your reply.
I use ILA to check the transaction, but address & data are corrected, and also the result in the PS is also corrected. It’ a amazing…
I guess the root cause may due to the PYNQ board restart…anyway, the problem is gone. thanks~