I hate to wake up this really old thread, but my question seems to fit it.
I thought I figured out how to use a ‘true dual port BRAM’ but I couldn’t get it to work. To isolate the problem I created a much smaller project that shows exactly where my problem lies.
The idea here is to write to the BRAM from the PS, and send the output of address 0 to the LEDs on my PYNQ-Z2. Although I can write to the BRAM from the PS side, and read back the correct data at the correct locations, I can not read from the PORTB side at all.
I tried the following:
- different clock connections, the one in this screenshot was just my last effort
- the ‘shared clock’ option
- connection a constant ‘1’ to ‘enb’
- connecting a constant ‘0’ to ‘rstb’
- setting the constant address to something else
The settings for the BRAM controller and BRAM itself are as shown in the tutorial.
I am using Vivado 2022.1 by the way.
So the problem is that I can never get any of the LEDs to light up. Connecting the address constant to the slice+LEDs does work obviously
I fairly certain I am missing something very obvious here, and would love hear what that is…
1 IP address is 13bit based and the other is 32bit based and how is the address map on the bram ctrl?
Thanks for answering! I noticed that too. This is how it is generated by the IP generator.
I figured it would ignore missing address lines and tie them to 0? I’ll check that.
I’ll also check if I can fix the mismatch somehow. I doubt it though, even though the BMG shows that it has 2048 words the incoming address is still 32 bits.
If I set the bram size to 4096 (the lowest value that Adress Editor allows) the address width changes (to bram_addr_a[11:0]), and the BMG then shows a write depth of 1024. The BMG address still shows 32 bit though. Would that be my problem here?
For N<32 to 32bit addressing, I will suggest to see how the warning message show the mapping is made.
While I am referring to the “Address Editor”.
If your address is set to 1K for example, but the BRAM itself is over 1K then there must be alignment issue.
Meantime, I will highly suggest use simple ILA to snoop into the address A, B. Data A, B. And sure things are correctly transferring.
Another thing is that the BRAM itself might require 2 cycle if registered output or even 3 cycle both Address and Data are registered accordingly.
I don’t thing you cannot make it addressably-alignable.
So my simple suggestions end here.
I will add ILA to try to see what’s going on.
Check the Vivado log for any warning messages. I suspect your design may have been optimized away and that you may have net/pin unconnected /has no load warning messages.
You mentioned you tried different options. I think you need to connect the ENB to constant 1.
You can open the elaborated view of the design, then the synthezied view. Check that the BRAM is instantiated, and that you can see connections to the LED pins. (However, if the signals are being remove, I expect there will be a warning in the Vivado log).
You could try remove the AXI GPIO controller while you debug this, as this may make the design slightly more difficult to analyze.