I’m having trouble building the base overlay for the 4x2. I’m running on Windows, and tried to follow the steps that the makefile would take in linux.
I’d like to rebuild the base image for the 4x2, to serve as a starting point for future development, following the instruction here:
“RFSoC-PYNQ/docs/rfsoc_4x2_base_overlay.md at master · Xilinx/RFSoC-PYNQ · GitHub”
- The documentation says to use vivado 2020.1, but the base.tcl file complains that it was made with version 2022.1 because this is line 25 of base.tcl:
set scripts_vivado_version 2022.1
- To test with 2022.1, I copied the board files from GitHub - RealDigitalOrg/RFSoC4x2-BSP to /mnt/c/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx
The tcl command get_board_parts seems to work:
get_board_parts 4x2
realdigital.org:rfsoc4x2:part0:1.0
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I installed the cmac license
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source build.tcl makes the design
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source build_bitstream.tcl runs a while, but ends with these lines:
WARNING: [Vivado 12-8222] Failed run(s) : ‘base_auto_us_df_0_synth_1’, ‘base_auto_cc_1_synth_1’, ‘base_util_vector_logic_0_synth_1’, ‘base_tx_fifo_0_synth_1’, ‘base_address_remap_0_0_synth_1’, ‘base_xbar_1_synth_1’, ‘base_auto_cc_0_synth_1’, ‘base_rx_fifo_0_synth_1’, ‘base_auto_pc_1_synth_1’, ‘base_auto_pc_0_synth_1’, ‘base_axi_smc_cmac_0_synth_1’, ‘base_cmac_0_synth_1’, ‘base_auto_ds_1_synth_1’, ‘base_m06_regslice_2_synth_1’, ‘base_m03_regslice_2_synth_1’, ‘base_m01_regslice_2_synth_1’, ‘base_m04_regslice_2_synth_1’, ‘base_m02_regslice_2_synth_1’, ‘base_m05_regslice_2_synth_1’, ‘base_m07_regslice_2_synth_1’, ‘base_auto_pc_9_synth_1’, ‘base_auto_pc_8_synth_1’, ‘base_auto_ds_2_synth_1’, ‘base_xbar_3_synth_1’, ‘base_axi_intc_0_0_synth_1’, ‘base_xbar_0_synth_1’, ‘base_auto_ds_0_synth_1’, ‘base_axi_dma_0_synth_1’, ‘base_m01_regslice_3_synth_1’, ‘base_s00_regslice_3_synth_1’, ‘base_m02_regslice_3_synth_1’, ‘base_m03_regslice_3_synth_1’, ‘base_xbar_6_synth_1’, ‘base_m04_regslice_3_synth_1’, ‘base_m05_regslice_3_synth_1’, ‘base_m00_regslice_3_synth_1’, ‘base_lmb_bram_if_cntlr_0_synth_1’, ‘base_mb_bram_ctrl_0_synth_1’, ‘base_mb_0_synth_1’, ‘base_xbar_5_synth_1’, ‘base_lmb_bram_0_synth_1’, ‘base_s00_regslice_2_synth_1’, ‘base_m00_regslice_2_synth_1’, ‘base_btns_gpio_0_synth_1’, ‘base_auto_us_1_synth_1’, ‘base_auto_pc_10_synth_1’, ‘base_auto_us_2_synth_1’, ‘base_xbar_4_synth_1’, ‘base_auto_us_0_synth_1’, ‘base_binary_latch_counter_0_0_synth_1’, ‘base_ila_0_0_synth_1’, ‘base_dff_en_reset_vector_0_0_synth_1’, ‘base_c_clk_mmcm_200_locked_0_synth_1’, ‘base_ddr4_0_sys_reset_0_synth_1’, ‘base_clk_mmcm_reset_0_synth_1’, ‘base_ddr4_0_0_synth_1’, ‘base_c_clk_mmcm_200_0_synth_1’, ‘base_clk_wiz_0_0_synth_1’, ‘base_intc_0_synth_1’, ‘base_intr_0_synth_1’, ‘base_dlmb_v10_0_synth_1’, ‘base_iic_0_synth_1’, ‘base_gpio_0_synth_1’, ‘base_ilmb_v10_0_synth_1’, ‘base_io_switch_0_synth_1’, ‘base_dlmb_v10_1_synth_1’, ‘base_mb_bram_ctrl_1_synth_1’, ‘base_rst_clk_wiz_1_100M_0_synth_1’, ‘base_timer_0_synth_1’, ‘base_intr_1_synth_1’, ‘base_iic_1_synth_1’, ‘base_intc_1_synth_1’, ‘base_io_switch_1_synth_1’, ‘base_gpio_1_synth_1’, ‘base_ilmb_v10_1_synth_1’, ‘base_lmb_bram_if_cntlr_1_synth_1’, ‘base_mb_1_synth_1’, ‘base_dff_en_reset_vector_0_1_synth_1’, ‘base_spi_0_synth_1’, ‘base_lmb_bram_1_synth_1’, ‘base_auto_pc_3_synth_1’, ‘base_xbar_2_synth_1’, ‘base_auto_pc_2_synth_1’, ‘base_auto_pc_4_synth_1’, ‘base_auto_pc_6_synth_1’, ‘base_auto_pc_7_synth_1’, ‘base_auto_pc_5_synth_1’, ‘base_rst_clk_wiz_1_100M_1_synth_1’, ‘base_timer_1_synth_1’, ‘base_pmod0_buf_0_synth_1’, ‘base_mdm_0_0_synth_1’, ‘base_pmod1_buf_0_synth_1’, ‘base_m07_regslice_3_synth_1’, ‘base_proc_sys_reset_0_0_synth_1’, ‘base_proc_sys_reset_1_0_synth_1’, ‘base_proc_sys_reset_2_0_synth_1’, ‘base_spi_1_synth_1’, ‘base_m06_regslice_3_synth_1’, ‘base_leds_gpio_0_synth_1’, ‘base_auto_cc_4_synth_1’, ‘base_xbar_11_synth_1’, ‘base_s01_data_fifo_3_synth_1’, ‘base_s00_mmu_0_synth_1’, ‘base_axi_dma_real_1_synth_1’, ‘base_xbar_12_synth_1’, ‘base_packet_generator_0_synth_1’, ‘base_auto_cc_5_synth_1’, ‘base_auto_cc_6_synth_1’, ‘base_s00_data_fifo_5_synth_1’, ‘base_axi_dma_imag_1_synth_1’, ‘base_axis_clock_converter_im_0_synth_1’, ‘base_axis_clock_converter_re_0_synth_1’, ‘base_s01_mmu_0_synth_1’, ‘base_xbar_7_synth_1’, ‘base_auto_pc_11_synth_1’, ‘base_auto_pc_13_synth_1’, ‘base_auto_ds_4_synth_1’, ‘base_auto_pc_12_synth_1’, ‘base_auto_ds_3_synth_1’, ‘base_auto_ds_5_synth_1’, ‘base_xbar_9_synth_1’, ‘base_axi_dma_imag_0_synth_1’, ‘base_axi_dma_real_0_synth_1’, ‘base_auto_cc_2_synth_1’, ‘base_xbar_8_synth_1’, ‘base_auto_cc_3_synth_1’, ‘base_xbar_10_synth_1’, ‘base_s01_data_fifo_4_synth_1’, ‘base_xbar_15_synth_1’, ‘base_packet_generator_1_synth_1’, ‘base_xbar_14_synth_1’, ‘base_auto_cc_8_synth_1’, ‘base_axis_clock_converter_re_1_synth_1’, ‘base_auto_cc_9_synth_1’, ‘base_s01_mmu_2_synth_1’, ‘base_axis_clock_converter_re_2_synth_1’, ‘base_axi_dma_imag_2_synth_1’, ‘base_s01_mmu_1_synth_1’, ‘base_packet_generator_2_synth_1’, ‘base_axi_dma_imag_3_synth_1’, ‘base_auto_cc_7_synth_1’, ‘base_xbar_17_synth_1’, ‘base_s00_data_fifo_6_synth_1’, ‘base_axi_dma_real_2_synth_1’, ‘base_s00_mmu_2_synth_1’, ‘base_auto_cc_11_synth_1’, ‘base_axis_clock_converter_im_1_synth_1’, ‘base_xbar_13_synth_1’, ‘base_s00_mmu_1_synth_1’, ‘base_auto_cc_10_synth_1’, ‘base_axis_clock_converter_im_2_synth_1’, ‘base_axi_dma_real_3_synth_1’, ‘base_xbar_16_synth_1’, ‘base_amplitude_controller_0_synth_1’, ‘base_axis_clock_converter_re_3_synth_1’, ‘base_zynq_ultra_ps_e_0_0_synth_1’, ‘base_axis_clock_converter_im_3_synth_1’, ‘base_proc_sys_reset_adc0_0_synth_1’, ‘base_util_ds_buf_0_0_synth_1’, ‘base_s00_mmu_3_synth_1’, ‘base_rfdc_0_synth_1’, ‘base_s01_data_fifo_5_synth_1’, ‘base_s00_data_fifo_7_synth_1’, ‘base_amplitude_controller_1_synth_1’, ‘base_packet_generator_3_synth_1’, ‘base_proc_sys_reset_adc2_0_synth_1’, ‘base_shutdown_lpd_0_synth_1’, ‘base_proc_sys_reset_dac2_0_synth_1’, ‘base_rgbleds_gpio_0_synth_1’, ‘base_sws_gpio_0_synth_1’, ‘base_system_management_wiz_0_0_synth_1’, ‘base_syzygy_std0_0_synth_1’, ‘base_xbar_18_synth_1’, ‘base_s01_mmu_3_synth_1’, ‘base_proc_sys_reset_dac0_0_synth_1’, ‘base_util_ds_buf_1_0_synth_1’
wait_on_runs: Time (s): cpu = 00:02:32 ; elapsed = 00:22:45 . Memory (MB): peak = 5559.840 ; gain = 60.648
# write_hw_platform -force -include_bit ./${overlay_name}.xsa
INFO: [Project 1-1937] No bit file available for ‘-include_bit’. To use this feature, run implementation through write_bitstream and then re-run write_hw_platform with ‘-include_bit’
INFO: [Project 1-1918] Creating Hardware Platform: c:/GQuEST/2024-03-10-4x2-base/RFSoC-PYNQ/boards/RFSoC4x2/base/base.xsa …
INFO: [Project 1-1906] Skipping semantic label enumeration.
WARNING: [BD 41-2589] Platform should have atleast one axi memory mapped master interface. Enable a master AXI interface as platform AXI_PORT.
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:01:08 ; elapsed = 00:08:22 . Memory (MB): peak = 5867.129 ; gain = 0.000
INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/Vivado/2022.1/data/embeddedsw) loading 0 seconds
ERROR: [Common 17-69] Command failed: Need an implemented design open to write bitstream. Aborting write_hw_platform…
