Hi, I am using PYNQ Z2. Manual says board contains dual 1MSPS ADC. Can we use both ADCs to sample the external analog signals. Does the signals should be differential or single ended. If yes how do we control them using the XADC IP wizard.
The Z2 board has an on-chip 1M/s ADC. The Vivado IP you will need to use is the XADC and you can read more about it at PG091. You will also want to visit this link to know the analogue interfacing details.
When you instantiate the XADC into a Vivado block diagram you will want to set it for Independent mode to be able to run both of its ADCs. However, the wizard will not be much help for that mode. I would recommend first starting to use the wizard in the Channel Sequencer mode and verifying the successful capture of your analogue signals and then re-visit enabling both ADCs.
How do you envision using these ADCs? One of the ADCs is usually devoted to system monitoring of the voltage rails and core temperatures. Even though it is a 1MS ADC, it is usually sampling multiple channels. The wizard helps define the channel arrangement for one ADC but you will have to craft your own RTL instance to enable the 2nd ADC. You can, however, use the RTL output as a guide and I recommend that.
You will also want to refer to the Z2 schematics at:
and the user manual where you can find the analogue pins…
Hi, Thanks for your reply.
I would like to use both the two ADCs independently sampling the external signals, can we achieve the required configuration using IP wizard. Can we use two ADCs to monitor external signals instead of one monitoring the on chip sensors. Can we enable both of them ?
As per zynq 7000 xadc manual in independent mode one ADC will monitor the on chip sensors, can this ADC be configured?
An excerpt from the ug480_7Series_XADC.pdf page 49
Auxiliary analog channels 0 to 7 are assigned to ADC A and are nominated as A channels. Auxiliary analog
channels 8 to 15 are assigned to ADC B and are nominated as B channels (see Figure 1-1, page 7). One A
channel and one B channel are always sampled and converted at the same time in simultaneous sampling
mode. Table 4-4 shows how A and B pairs are selected using sequencer channel register 49h. Other
sequencer registers that define averaging, analog input mode, and settling time are also available for use in
My question is which GPIOs(Signal names) are connected to ADC B and ADC A in PYNQ z2 Board.
The XADC Wizard is rather limited and best for single channel or the channel sequencer setup. I would recommend studying the RTL that it creates (VHDL or Verilog) and then build upon on it to craft the Independent mode you actually do want. A nice feature is that you can actually simulate the XADC before you do trial and error with your board. This will help you clarify a lot of the ambiguity that I also find from the documentation. The documentation for the XADC used in the Zynq itself is under the 7series documentation. I’ll include it here for easy reference:
I interpret the following according to UG480 and Figure 1-1:
The Temperature and Supply sensors are only sampled by ADC A. ADC A can have its own channel sequence defined at run-time or DRP to sample VP_0/VN_0 and the VAUX channels. ADC B can also have its own channel sequence sampling VP_0/VN_0 and any of the VAUX channels.
Figure 1 shows the following:
The Z2 only brings in 6 pins of analogue signals. If in bipolar mode then you just get 3 signals to sample. The pins were listed in the TUL Table of the Z2 datasheet which correspond to the Arduino header.
I’ll have to see what examples from the Xilinx Wiki I can find regarding the available software to setup the sequencer. In a past design I had just used the DRP to sample a known set of analogue inputs. I can hack at it abit by using the XADC wizard and setting it AXILite for configuration and hopefully we can configure it with the driver and take some samples. I recommend also checking out this page as well:
I will have to further research and develop a PYNQ example but hopefully this can get you started…
So I think that you have flexibility of assigning the VAUX_n signals to either ADC A or ADC B. The other Figure 4-4 is referring to external mux option. The only ones restricted are the internal sensors to ADC A in this case.