Using XADC in Independent (Dual Channel Sampling) Mode

Hey all,

I’m working on a project that requires me to do a number of things. In bullet point form, I’m trying to:

  • Run the XADC in Independent mode, allowing me to sample two channels simultaneously
  • Stream the XADC data over an AXI Stream into DMA
  • Process the results.

My initial set of questions is trying to set the XADC up properly. How do the analog inputs of the Pynq Z2 board work? Is the Vx_n pin always tied to an analog ground, or is that set somewhere else on the board? I’m assuming the “simple” way of thinking about this is to have the Vx_p pin tied to the analog input pin and the Vx_n pin tied to the analog output, so in this case Vaux5_p is tied to A4 and Vaux13_p is tied to A5, and I would use those pins accordingly, but my first question is where are Vaux5_n and Vaux13_n tied to?

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@kirby

https://docs.xilinx.com/r/en-US/ug480_7Series_XADC/XADC-Overview

I am aware of the documentation, I’ve looked it over already. I’m not asking about what the XADC IP is doing, I’m asking where the pins on the Pynq Z2 board are going.


My understanding is based on the base.xdc file and the above graphic, J20 and G19 are tied to Vaux5_p and Vaux13_p respectively, but I don’t see where H20 (Vaux5_n) or G19 (Vaux13_n) are pinned to.

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@kirby

Read document and sure you understand the document first.
Your questions had covered in this document.

ENJOY~

Hi @kirby,

I suggest you check the schematics for further clarification.
These can be found on the manufacturer webpage.

https://www.tulembedded.com/fpga/ProductsPYNQ-Z2.html

Mario

@marioruiz

Mario I think you are directing the poster to a disappointment.
Dipolar and unipolar is what fixed on the hardware of PYNQ-Z2 board.
I shouldn’t make this much clear MY BAD

ENJOY~

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