Changing Sampling Frequency of RFDC IP

[Riya_Sachdeva]

Hello! I’m studying this design: RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub

I made a reduced version to only run the DAC to ADC loopback example on the RFDC IP:

Radio Hierarchy:

I’m trying to change the sampling frequency of the RFDC IP. The original was 4.91 GHz. I’m trying to run it at 2.4576 GHz.
These are the RFDC Settings:

ADC:

DAC:

I have also changed PL1 Clock (generated by PS) to 150 MHz instead of 300 MHz:

The clock wizard now generates 155 MHz instead of 310 MHz.

This is the register file for LMX frequency of 245.76 MHz, for LMK frequency of 245.76 MHz:

R112	0x700000
R111	0x6F0000
R110	0x6E0000
R109	0x6D0000
R108	0x6C0000
R107	0x6B0000
R106	0x6A0000
R105	0x690021
R104	0x680000
R103	0x67D555
R102	0x663F97
R101	0x650011
R100	0x640000
R99	0x632AAB
R98	0x6201A0
R97	0x610888
R96	0x600000
R95	0x5F0000
R94	0x5E0000
R93	0x5D0000
R92	0x5C0000
R91	0x5B0000
R90	0x5A0000
R89	0x590000
R88	0x580000
R87	0x570000
R86	0x565879
R85	0x55F458
R84	0x540001
R83	0x5354C9
R82	0x523161
R81	0x510000
R80	0x504000
R79	0x4F001F
R78	0x4E0003
R77	0x4D0000
R76	0x4C000C
R75	0x4B09C0
R74	0x4A0000
R73	0x49003F
R72	0x480001
R71	0x470081
R70	0x46C350
R69	0x450000
R68	0x4403E8
R67	0x430000
R66	0x4201F4
R65	0x410000
R64	0x401388
R63	0x3F0000
R62	0x3E0322
R61	0x3D00A8
R60	0x3C0000
R59	0x3B0001
R58	0x3A9001
R57	0x390020
R56	0x380000
R55	0x370000
R54	0x360000
R53	0x350000
R52	0x340820
R51	0x330080
R50	0x320000
R49	0x314180
R48	0x300300
R47	0x2F0300
R46	0x2E07FC
R45	0x2DC0CC
R44	0x2C0C22
R43	0x2B0000
R42	0x2A0000
R41	0x290000
R40	0x280000
R39	0x270001
R38	0x260000
R37	0x250204
R36	0x240020
R35	0x230004
R34	0x220000
R33	0x211E21
R32	0x200393
R31	0x1F43EC
R30	0x1E318C
R29	0x1D318C
R28	0x1C0488
R27	0x1B0002
R26	0x1A0DB0
R25	0x190C2B
R24	0x18071A
R23	0x17007C
R22	0x160001
R21	0x150401
R20	0x14E048
R19	0x1327B7
R18	0x120064
R17	0x11012C
R16	0x100080
R15	0x0F064F
R14	0x0E1E70
R13	0x0D4000
R12	0x0C5001
R11	0x0B0018
R10	0x0A10D8
R9	0x090604
R8	0x082000
R7	0x0740B2
R6	0x06C802
R5	0x0500C8
R4	0x040C43
R3	0x030642
R2	0x020500
R1	0x010809
R0	0x00259C

For all other settings I have tried, the board crashes because of incorrect clock network. This is the only configuration in which the design works. However, it only collects real samples of data, and not imaginary ones. These are the output graphs:

Even channels 0 and 1, which are not given any input and are expected to collect garbage data, are not collecting imaginary samples. Please let me know if you have any ideas about how I can fix this issue, and also how I can change the sampling frequency to values which are not multiples of 245.76 MHz.

[matthew]

Hi,
For your python code, did you use the same jupyter notebook
(RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub)
or did you modify some lines?

[Riya_Sachdeva]

Hello,
I changed the line

base.init_rf_clks()

to

base.init_rf_clks(lmx_freq = 245.76)

[matthew]

You created a new block design. How did you implement it in your board?
Did you call the bitstream base.bit?

[Riya_Sachdeva]

I changed the name of the bitstream to base_fs_2_4576.bit. I have changed the import code slightly to import all the necessary files from the local folder instead of site-packages folder. That part seems to be working fine, I have used it in multiple variations of the same design.

[Riya_Sachdeva]

This is one working variation in which I replaced the amplitude controller and packet generator IPs with custom HLS IPs: https://youtu.be/tGLuYzdgQBw?feature=shared

[matthew]

About the no imaginary part issue, have you tested with the overlay provided by AMD? To check if there is no component issue, if the issue is only in software and not hardware.
The notebook provided by AMD should work with the base overlay they provided: (RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub)

[Riya_Sachdeva]

Yes, that works. The problem only arises when I change the sampling frequency.

[matthew]

In the DUC 0 configuration, is it normal that the Analog Output Data is “real”? Can it be switched to “I/Q”?
Same question for the Mixer mode in the “Mixer setting” of the same image

[Riya_Sachdeva]

They can be changed. I’ve found one alternate DAC configuration which did not throw any errors, I’m going to try it tomorrow.

[ZhimuG]

Hi Riya, I’m very interested in how you program the LMX and LMK clocks, and am wondering could you share what program you used to program these clocks, and if you have any good references to how to program them? Thank you very much!

Zhimu

[Riya_Sachdeva]

I tried the new DAC configuration, and it is giving the same result.

[Riya_Sachdeva]

Hi Zhimu,
I used TICS Pro to generate the register map for the LMX clocks. The LMK clock is fixed to 245.76 MHz. You can refer to these videos: https://youtu.be/1pbDMXj_aP4?feature=shared, https://youtu.be/Usq0waJMJvw?feature=shared, https://youtu.be/pJqzpnLTuKQ?feature=shared

[matthew]

@Riya_Sachdeva

how I can change the sampling frequency to values which are not multiples of 245.76 MHz

@Riya_Sachdeva

I’m trying to change the sampling frequency of the RFDC IP. The original was 4.91 GHz. I’m trying to run it at 2.4576 GHz.

Do you have the issue for sampling frequency as multiples of 245.76 MHz because you changed the sampling rate to 2.4576GHz?

[Riya_Sachdeva]

Well I’m not even able to get proper results for 2.4576 GSPS so I haven’t tried any other sampling rate.

[Riya_Sachdeva]

I believe for other sampling frequencies I will have to generate new LMX register values, I’m not sure if I will have to make any other changes in the design.

[matthew]

@Riya_Sachdeva

I have also changed PL1 Clock (generated by PS) to 150 MHz instead of 300 MHz:

Why have you changed this clock? Did you want to reduce the PL clock because you reduced the sampling frequency?

[Riya_Sachdeva]

Yes that was the intention, but I changed it back to 300 MHz and still got the same results. Imaginary outputs are 0.

[matthew]

If I understand correctly, you receive an imaginary part with the base overlay of AMD.
Then, you reduced that overlay (you modified the block design) and you changed the frequency settings. Your received signals are now without imaginary part.

Did you try going back to the base overlay of AMD, apply the frequency setting modifications, and test if you can still get an imaginary part? To be sure that your design reduction did not impact a configuration

[Riya_Sachdeva]

Yeah the design is working. The imaginary part becomes 0 only when I change the sampling frequency to 2.4576 GSPS in the rfdc settings, and set LMX frequency as 245.76 MHz. The original design has LMX frequency = 491.52 MHz and sampling frequency = 4.9152 GSPS.