I’m working with ZCU208 boards, and have run into what may be a limiting issue for my implementation.
I realize that these devices are optimized for testing RF computations, and as such the CLK104 board is tuned to minimize short-term high-frequency clock jitter that might affect sample-to-sample inputs and outputs.
For my purposes, however, I needed the high sampling rate and ADC/DAC integration, but I also need the timebase to be stable over long periods of time, with the assumption rather that the high-frequency jitter averages out over the timescales of my measurements.
I’ve found that, when clocked by a rubidium standard external reference, the SYSREF output drifts by a LOT over the course of a day – after one day, it’s a couple hundred microseconds of total timing drift.
Has anyone else found this to be the case? If so, how were you able to fix it? Are there better values for the Rdivs, Ndivs, or various gains of the CLK104 PLLs that I might be able to change to affect better performance in its long-term stability?
Or is this a wash, and there’s just no way to do so with the CLK104? If this is the case, has anyone found it possible to discipline the board via the SYNC_IN port, or perhaps found an alternative daughter board for these eval kits that has better locking for the micro- to mHz frequency ranges?
Many thanks,
Reid