Trouble with the RF Data Converter -- Frequency offset, low power output?

ZCU208 RFSoC, latest version of PYNQ.

I’ve been running into some strange behavior in the outputs of the FPGA Evaluation Board. I wired up a quick DDS compiler in my block design to run test cases.

In the Jupyter server, I run xrfclk.set_ref_clks(lmk_freq=245.76, lmx_freq=409.6), and set the reference clock on the RFDC to match:

The RFDC overlay IP imports correctly, with the relevant tiles and blocks initializing identically, with the DACVOP all set to the maximum value of 40500:

Then, some quick conversion:

fclk = 128.0
fsig = 4
PIR_SET = round(pow(2,32)*fsig/fclk)

and I write the PIR_SET value into an AXI register via MMIO, which then feeds the S_AXIS_PHASE input of the DDS compiler.

The output is perfectly aligned with what one expects. 32 clock cycles per wave. Exactly 4MHz, when generated by the 128MHz clock output by the primary DAC channel.

Now… the issues.

When measured on an oscilloscope with a 50Ohm probe, matching the impedance of a balun filter I have built myself (the RF transformers that were provided with the ZCU208 only go down to 10MHz), the output signal is barely visible.

Swapping to a 1MOhm probe shows the signal a bit more clearly:

The signal is, for some reason, more negative than positive. Additionally, it’s weak; only 130mVpp.
This is a signal that’s spanning the full 16-bit signed range of the DAC, and, according to the DS926 data sheets on the electrical characteristics of the DAC, should correspond to 4.5dBm, or 1.05Vpp.

Other signals that I’ve output from the DAC have been similarly weak.

The real kicker here, though, is a constant, proportional ~6% decrease in output frequency. Increasing the set frequency in Jupyter to 10MHz reveals a 9.4MHz wave on the oscilloscope.

All other signals I generate and feed through the RFSoC experience a similar drop in frequency.

Is this a problem with the analog electronic frontend? I’ve tried using different balun filters, including those on the XM655 breakout card with >10MHz signals running through them.

I’ve measured the stability of the 7.68MHz reference clock too. It is indeed measured at 7.68MHz, but its phase spectral density compared to the Moku:Pro I’m using is… bad…

What’s the dealio here?

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Ok, I’m pretty sure the thing with the weak signal was a crap cable. Swapping it out fixed the issue there. However, the frequency drop I mentioned at the end is still a worrier. I programmed another board with the same bitstream, same cable setup, same signals in, same output settings, and the spectral density was orders of magnitude better, and the frequency offset disappeared. Could this be an issue with the CLK104 board? The phase noise of the SYSREF output clock is crap, so perhaps some internal PLL isn’t closing… I sincerely hope it isn’t; I have no clue how I would begin troubleshooting that.

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The performance of the setup on the other board was also enormously improved by locking to a 10MHz reference provided by the device I’m using to generate and measure my analog signals.
(Xrfclk configuration | LMK04828 | Using external 10MHz reference clock - #11 by JasonPhysics).
It would be really great, however, if I could fix the issues with the first board; I need them both.

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