CNN on pynq (using RTL)

[kongming]

I want to implement a simple CNN operation (e.g. Convolution, Fully connected layer) using PYNQ. However, Most online resources use HLS to design the hardware and generate a BIT file, which is then implemented in RTL. However, I want to design the hardware directly in RTL and use it as a PYNQ overlay. Are there any reference codes or examples for this approach?

Also I want to utilize the following url to make convolution code. but it is hard to transfer any array element using AXI4. please help to solve this problem

Tutorial: Creating a new Verilog Module Overlay

This is a tutorial targeted at Verilog and Python users who wish to use Zynq 7000 to do Verilog FPGA module development and interface their Verilog in the PL to the PS system. I went through this learning curve a few months ago and wanted to share my experience to “pay it forward”. I used a TUL-2 Board. Design Steps and decisions The general flow of design steps I followed are: Develop the IP. You will interface to your IP through a memory mapped interface. Instance the IP in an AXI IP Wrappe…