After exploring the Xilinx built composable overlay coming as standard with the Kria KV260 board it provides a very helpful video processing tool for live video. However, when streaming with USB camera to display port the latency is moderately high latency between the displayed frame and real-time.
I want to do some investigation with the KR260 I have available in an attempt to stream video with greatly reduced latency using its ethernet ports that feed directly into the programmable logic. My understanding is that if I can bypass the return of the Video stream to the Processing system (PS) via the VDMA, by streaming video straight out of the programmable logic via the ethernet to a compatible display such as a ScioTeq display (SV-340 | Scioteq) It should reduce the noticeable latency of the output.
My understanding is also that the USB serial input is to the PS which then introduces an input latency which would need resolved. Could you effectively stream a frame in and out of the programmable logic without interference from the PS with the KR260 ethernet arrangement?
The issue comes as the composable overlay is tailored for the KV260 (understandable as it is marketed as the vision processing boards). However, my question Is: if I wanted to rebuild the composable Overlay for the KR260, would it be as easy as opening the composable overlay design in vivado, change the boards and parts to the KR260 and then adding in the constraint files applicable for the KR260.
If anyone has any insight feel free to respond,
Thanks,
Cameron
if I wanted to rebuild the composable Overlay for the KR260, would it be as easy as opening the composable overlay design in vivado, change the boards and parts to the KR260 and then adding in the constraint files applicable for the KR260.
Changing the board will be the first step, but it is not the only one. You will also need to remove the MIPI hierarchy as this interface is not available on the KR260.
Could you effectively stream a frame in and out of the programmable logic without interference from the PS with the KR260 ethernet arrangement?
If you are capturing from USB not really, if the capture happens in the PL the PS is not needed. For instance, the IAS MIPI sensor interfaces (we don’t have an example for this on PYNQ) or the Raspberry Pi camera interface (we support the Digilent PCAM5C) on the KV260.
Or the x1 SLVS-EC Gen2 x2 lane interface on the KR260.
Would this require an additional interace in the Vivado design that replicates the action of the MIPI interface but for the SVLS-EC? The above documentation describes a prebuilt SLVS-EC RX IP Core which I think should be suitable?
This monitor is just a 1080P display.
Use SSD2828 or similar interface IC is more easier and make life easier.
AML055-FHD-056A
I had used before and nice and simple MIPI CSI-2 via SSD2828 neat and stable.
Would this require an additional interace in the Vivado design that replicates the action of the MIPI interface but for the SVLS-EC? The above documentation describes a prebuilt SLVS-EC RX IP Core which I think should be suitable?
Yes, this would require the logic in the PL to capture the images from the sensor and probably some control on the PS as well. I am not familiar with that IP neither this particular camera, so the Xilinx forums may be a better place to ask for support.
